ISP1505CBS,551 NXP Semiconductors, ISP1505CBS,551 Datasheet - Page 51
ISP1505CBS,551
Manufacturer Part Number
ISP1505CBS,551
Description
RF Transceiver USB2.0 ULPI HOST/DEV
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1505ABS557.pdf
(76 pages)
Specifications of ISP1505CBS,551
Operating Supply Voltage
1.65 V to 3.6 V
Mounting Style
SMD/SMT
Package / Case
HVQFN-24
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935278317551 ISP1505CBS-S
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NXP Semiconductors
Table 38.
Table 39.
Table 40.
ISP1505A_ISP1505C_3
Product data sheet
Bit
7 to 2
1
0
Bit
7 to 0
Bit
Symbol
Reset
Access
Symbol
SCRATCH
[7:0]
Debug register (address R = 15h) bit description
Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description
Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation
10.1.10 Scratch register
10.1.11 Reserved
10.1.12 Access extended register set
10.1.13 Vendor-specific registers
10.1.14 Power Control register
R/W/S/C
Symbol
-
LINESTATE1
LINESTATE0
7
0
Table 39
purposes.
Registers 19h to 2Eh are not implemented. Operating on these addresses will have no
effect on the PHY.
Address 2Fh does not contain register data. Instead it links to the extended register set.
The immediate register set maps to the lower end of the extended register set.
Addresses 30h to 3Fh contain vendor-specific registers.
Table 40
Access
R/W/S/C
R/W/S/C
6
0
shows the bit description of the Scratch register. It is an empty register for testing
provides the bit allocation of the Power Control register.
reserved
Value
00h
Description
reserved
Line State 1: Contains the current value of LINESTATE 1
Line State 0: Contains the current value of LINESTATE 0
R/W/S/C
5
0
Rev. 03 — 26 August 2008
Description
Scratch: This is an empty register byte for testing purposes. Software
can read, write, set and clear this register. The functionality of the PHY
will not be affected.
R/W/S/C
4
0
ULPI HS USB host and peripheral transceiver
BVALID_
R/W/S/C
FALL
3
0
ISP1505A; ISP1505C
BVALID_
R/W/S/C
RISE
2
0
reserved
R/W/S/C
1
0
© NXP B.V. 2008. All rights reserved.
IGNORE_
R/W/S/C
RESET
0
0
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