AX5151-TSSOP24-TU AXSEM, AX5151-TSSOP24-TU Datasheet - Page 25

• Manufacturer Part Number: AX5151-TSSOP24-TU
• Description: RF Transmitter TSSOP-Class-IC
• Manufacturer: AXSEM
• Type: Single Chip Transceiverr

Specifications of AX5151-TSSOP24-TU

• Package / Case: TSSOP-24
• Operating Frequency: 400 MHz to 940 MHz
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.3 V to 3.6 V
• Supply Current: 100 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.10. Framing and FIFO
Most radio systems today group data into packets. The framing unit is responsible for
converting these packets into a bit-stream suitable for the modulator, and to extract packets
from the continuous bit-stream arriving from the demodulator.
The Framing unit supports four different modes:
The micro-controller communicates with the framing unit through a 4 level × 10 bit FIFO. The
FIFO decouples micro-controller timing from the radio (modulator and demodulator) timing.
The bottom 8 bits of the FIFO contain transmit or receive data. The top 2 bit are used to
convey meta information in HDLC and 802.15.4 modes. They are unused in Raw and Raw
with Preamble Match modes. The meta information consists of packet begin / end
information and the result of CRC checks.
The AX5151 contains one FIFO. Its direction is switched depending on whether transmit or
receive mode is selected.
The FIFO can be operated in polled or interrupt driven modes. In polled mode, the micro-
controller must periodically read the FIFO status register or the FIFO count register to
determine whether the FIFO needs servicing.
In interrupt mode EMPTY, NOT EMPTY, FULL, NOT FULL and programmable level interrupts are
provided. The AX5151 signals interrupts by asserting (driving high) its IRQ line. The interrupt line
is level triggered, active high. Interrupts are acknowledged by removing the cause for the
interrupt, i.e. by emptying or filling the FIFO.
Basic FIFO status (EMPTY, FULL, Overrun, Underrun, and the top two bits of the top FIFO word)
are also provided during each SPI access on MISO while the micro-controller shifts out the
register address on MOSI. See the SPI interface section for details. This feature significantly
reduces the number of SPI accesses necessary during transmit and receive.
Version 1.0
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HDLC
Raw
Raw with Preamble Match
802.15.4 compliant
Circuit Description
Datasheet AX5151
25