AX5043-QFN28-TU AXSEM, AX5043-QFN28-TU Datasheet
AX5043-QFN28-TU
Specifications of AX5043-QFN28-TU
Related parts for AX5043-QFN28-TU
AX5043-QFN28-TU Summary of contents
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... DATASHEET AX5043 Advanced high performance ASK and FSK narrow-band transceiver for 70-1050 MHz range Version 0.2 Preliminary ...
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... Version 0.2 Preliminary Datasheet AX5043 ...
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... Document Type Datasheet Document Status PRELIMINARY/CONFIDENTIAL Document Version Version 0.2 Product AX5043 Version 0.2 Preliminary 3 Table of Contents Datasheet AX5043 ...
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... General Purpose ADC (GPADC) ................................................................................................ Circuit Description ....................................................................................... 22 ! 5.1. Voltage Regulators.................................................................................................................. 23 ! 5.2. Crystal Oscillator ..................................................................................................................... 24 ! 5.3. Low Power Oscillator and Wake on Radio (WOR) Mode........................................................... 24 ! 5.4. GPIO Pins................................................................................................................................. 24 ! 5.5. SYSCLK Output ........................................................................................................................ 25 ! 5.6. Power-on-reset (POR) .............................................................................................................. 25 ! 5.7. RF Frequency Generation Subsystem ..................................................................................... 25 VCO ......................................................................................................................................... 26 VCO Auto-Ranging ................................................................................................................... 26 Version 0.2 Preliminary ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! Datasheet AX5043 ...
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... Using a Dipole Antenna and the internal TX/RX Switch ........................................................... 47 Using a single-ended Antenna and the internal TX/RX Switch ................................................. 48 Using an external high-power PA and an external TX/RX Switch ............................................. 49 Using the single-ended PA ....................................................................................................... 50 Using two Antenna .................................................................................................................. 51 Using an external VCO inductor............................................................................................... 52 Using an external VCO............................................................................................................. 53 Using a TCXO........................................................................................................................... 54 Version 0.2 Preliminary 5 Table of Contents ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! Datasheet AX5043 ...
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... Table of Contents ! 8. QFN28 Package Information .......................................................................... 55 ! 8.1. Package Outline QFN28........................................................................................................... 55 ! 8.2. QFN28 Soldering Profile .......................................................................................................... 56 ! 8.3. QFN28 Recommended Pad Layout .......................................................................................... 57 ! 8.4. Assembly Process.................................................................................................................... 57 Stencil Design & Solder Paste Application ............................................................................... Life Support Applications .............................................................................. 59 ! 10. Contact Information ..................................................................................... 60 Version 0.2 Preliminary ! ! ! ! ! ! ! ! Datasheet AX5043 ...
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... Supports also packet sizes > • 256 Bytes Ability to store RSSI, frequency • offset and data-rate offset with the packet data 256 bytes packet buffer or FIFO • SPI micro-controller interface • Extended AXSEM register set • Advanced Crystal Oscillator Preliminary 7 Table of Contents Datasheet AX5043 ...
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... FCC CFR part 90 for 6.25 kHz, 12.5 kHz and 25 kHz narrow-band standards Suited for systems targeting • compliance with Wireless M-Bus standard EN 13757-4:2005 Version 0.2 AMR • Security • Messaging / Paging • Wireless Sensors • Remote controls • Preliminary Datasheet AX5043 ...
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... RF Frequency - 10&2 Generation Subsystem RF Output 70 MHz – 1GHz Crystal Oscillator Divider typ. 16 MHz "3 " Figure 1 Functional block diagram of the AX5043 Version 0.2 AX5043 IF - De- channel modulator filter Modulator Chip configuration POR References Low Power Oscillator 640 Hz/10 kHz Voltage ...
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... Can be programmed to be used as a general purpose I/O pin Selectable internal 65 k! pull-up resistor N Must be left unconnected P Power supply 1.8 V – 3 Must be left unconnected A GPADC input A GPADC input A Crystal oscillator input/output A Crystal oscillator input/output P Ground on center pad of QFN, must be connected Preliminary Datasheet AX5043 ...
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... Pin-out Drawing VDD_ANA 1 GND 2 ANT ANTN 5 ANTP1 GND 6 VDD_ANA 7 Figure 2: Pin-out drawing (Top view) Version 0.2 I/O = digital input/output signal N = not to be connected P = power or ground ANTSEL 20 PWRAMP 19 IRQ AX504 MOSI 16 MISO 15 CLK Preliminary 11 Pin Function Descriptions Datasheet AX5043 ...
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... T Operating temperature amb T Storage temperature stg T Junction Temperature j Version 0.2 CONDITION MIN -0.5 -10 -100 -0.5 -0.5 HBM -2000 -40 -65 Preliminary MAX UNIT 5.5 V 100 mA 800 mW 15 dBm 10 mA 100 5.5 V 5.5 V 2000 V 85 °C 150 °C 150 °C Datasheet AX5043 ...
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... MHz, 0 dBm, ASK 868 MHz, 10 dBm, FSK 868 MHz, 0 dBm, FSK 868 MHz, -10 dBm, FSK 868 MHz, 10 dBm, ASK 868 MHz, 0 dBm, ASK Preliminary 13 Specifications TYP MAX. UNIT . - °C 1.8 3.0 3 300 nA 400 230 ! tbd tbd Datasheet AX5043 ...
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... Digital Outputs I Output Current, high OH I Output Current, low OL I Tri-state output leakage current OZ Version 0.2 CONDITION MIN. TYP. 1.9 1.2 2.0 -10 Pull-ups enabled in the relevant 65 pin configuration registers VDD_IO= 2.4V OH VDD_IO= 0.4V OL -10 Preliminary MAX. UNIT k" Datasheet AX5043 ...
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... XTALCAP = 0x01 – 0xFF Note 3 / XTAL CONDITION LPOSC FAST=0 LPOSC FAST=1 Internal calibration vs. crystal clock has been performed Preliminary Specifications MIN. TYP. MAX. UNIT 16 MHz MHz 0 k" MIN. TYP. MAX. UNIT 608 640 672 Hz 9.8 10.2 10.8 kHz Datasheet AX5043 15 ...
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... MHz, 300 kHz from carrier 868 MHz, 1 MHz from carrier 433 MHz, 100 kHz from carrier RFDIV=1 70 RFDIV=0 140 Preliminary TYP MAX UNIT . . 16 MHz 2168 !A 525 MHz 1050 0.98 Hz 100 200 kHz 500 -100 dBc/Hz -110 -125 -112 dBc/Hz 400 MHz 800 Datasheet AX5043 ...
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... L =15 nH 54, RFDIV Note: The external VCO 70 frequency needs to be 2xf RF 0 Available at FILT in external 0 loop filter mode vs L vco ext Preliminary 17 Specifications 380 MHz 7.5 MHz/V -120 dBc/Hz -130 1000 MHz tbd " 0.7 V 1.8 V 1.8 V ext Datasheet AX5043 ...
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... Emission @ 2 harmonic harm2 PTX 868- rd Emission @ 3 harmonic harm3 Notes 1. 2. Additional low-pass filtering was applied to the antenna interface, see section 7: Application Information. Version 0.2 CONDITION MIN. TYP. 1 -10 Note 1 -50 Note 2 -55 Preliminary MAX. UNIT 75 kbps 15 dBm 0.5 dB dBc Datasheet AX5043 ...
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... FSK 0.5, 10 kbps FSK 0.5, 1 kbps 2 tones separated by 100 kHz reading register RSSI FSK 4.8 kbps, h= 0.5, 25 kbps channels Note 1 FSK 4.8 kbps, Note 2 Preliminary 19 Specifications TYP. MAX. UNIT 1 100 kbps -106 -116 dBm -126 -20 dBm -35 dBm tbd tbd tbd dB tbd Datasheet AX5043 ...
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... DATA output change relative to Tdco active DCLK edge For a figure showing the wire-mode interface timing parameters see section 5.17: Wire-Mode Interface. Version 0.2 CONDITION MIN. TYP Note CONDITION MIN. TYP. Depends on bit- 1.6 rate programming Preliminary MAX. UNIT MAX. UNIT 10000 ! Datasheet AX5043 ...
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... Integral non linearity DNL Differential non linearity Z Input Impedance in V Input DC level DC-IN Input signal range in differential V IN-DIFF mode Input signal range in single-ended V IN-SE mode Version 0.2 CONDITION MIN. TYP. 0. Preliminary 21 Specifications MAX. UNIT 10 bit 1 MS LSB 1 LSB 50 k" 0 Datasheet AX5043 ...
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... In frame-mode data is sent and received via the SPI port in frames. Pre- and post-ambles as well as checksums can be generated automatically. Interrupts control the data flow between a micro- controller and the AX5043. In wire-mode the IC behaves as an extension of any wire. The internal communication controller is disabled and the modem data is directly available on a dedicated pin (DATA). The bit clock is also output on a dedicated pin (DCLK) ...
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... This will initiate startup and reset of the held low during initialization and will rise to high at the end of the initialization, when the chip becomes ready for operation. Version 0.2 AX5043. Then the MISO line should be polled will be Preliminary 23 Circuit Description Datasheet AX5043 ...
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... Pins DATA, DCLK, SYSCLK, IRQ, PWRAMP, ANTSEL can be used as general purpose I/O pins by programming pin configuration registers PINFUNCIRQ PINFUCNANTSEL , PINSTATE . Pull-ups are disabled if output data is programmed to the GPIO pin Version 0.2 XTALCAP . PINFUNCSYSCLK PINFUNCDCLK , PINFUNCPWRAMP , . Pin input values can be read via register Preliminary PINFUNCDATA , , Datasheet AX5043 ...
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... RX/TX switching, this enables low-power system design. For receive operation the RF frequency is fed to the mixer, for transmit operation to the power- amplifier. Version 0.2 Figure 5 GPIO pin PINFUNCSYSCLK register set the divider ratio. The SYSCLK PWRMODE register. Preliminary 25 Circuit Description Datasheet AX5043 ...
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... VCO. Version 0.2 FREQ registers. For operation in the 433 MHz PLLVCODIV register must be programmed. register ranges the frequency in register ranges the frequency in PLLLOOP Preliminary PLLVCODIV PLLRANGINGA or FREQA , while setting FREQB . The RNGERR bit the charge pump current can be Datasheet AX5043 ...
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... IF-Channel-Filter and Demodulator The IF-channel-filter and the demodulator extract the data bit-stream from the incoming IF signal. They must be programmed to match the modulation scheme as well as the data-rate. Inaccurate programming will lead to loss of sensitivity. Version 0.2 MODECFGA . TXPWRCOEFFB MODECFGA. Preliminary 27 Circuit Description . Datasheet AX5043 ...
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... Circuit Description The channel filter offers bandwidths of 995 221 kHz. To calculate the optimal settings use the AXSEM AX5043 configuration software. Version 0.2 Preliminary Datasheet AX5043 ...
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... IRQ line. The interrupt line is level triggered, active high. Interrupts are acknowledged by removing the cause for the interrupt, i.e. by emptying or filling the FIFO. Version 0.2 ENCODING . To calculate the optimal settings use Preliminary 29 Circuit Description Datasheet AX5043 ...
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... The packet length with a byte indicating the length of the packet. In packet-modes a CRC can be computed automatically. HDLC Mode is the main framing mode of the AX5043. In this mode, the 1 automatic packet-delimiting and optional packet-correctness-check by inserting and checking a cyclic redundancy check (CRC) field. ...
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... When it detects the preamble, it aligns the de-serialization to it. The preamble can be between 4 and 32 bits long. 5.12. RX AGC and RSSI The AX5043 features a digital receiver signal strength indicator (RSSI). The RSSI can be read in the RSSI register and has a resolution steps. Version 0.2 Preliminary 31 Circuit Description Datasheet AX5043 ...
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... BW=BIT-RATE BW=(1+h) #BIT-RATE "f=+f deviation deviation 0 0 BW=BIT-RATE "$=180 can demodulate signals with h < 32. AX5043 to synchronize the receiver frequency to a carrier signal. For AFC . Preliminary Max. Bit-rate 75 kBit/s 75 kBit/s 75 kBit/s deviation supports OQPSK. However, unless AX5043 has a frequency Datasheet AX5043 ...
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... To leave DEEPSLEEP mode the pin SEL has to be pulled low. This will initiate DEEPSLEEP startup and reset of the AX5043. Then the MISO line should be polled will be held low during initialization and will rise to high at the end of the initialization, when the chip becomes ready for operation. ...
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... The settling time is dominated by the crystal used, typical value 3ms. 3 FULLTX Data transmission 4 POWERDOWN PWRMODE A typical sequence for a receive session: Step PWRMODE Remarks 1 POWERDOWN 2 STANDBY The settling time is dominated by the crystal used, typical value 3ms 3 FULLRX Data reception 4 POWERDOWN Version 0.2 Preliminary Datasheet AX5043 ...
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... GPADC INTERRUPT PENDING 15 S0 DSP INTERFACE INTERRUPT PENDING Note: Bit cells 8-15 (S7…S0) are only available in two address byte SPI access formats. Version 0.2 AX5043 are programmed via the serial AX5043 outputs the most important status bits. This Preliminary 35 Circuit Description Datasheet AX5043 ...
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... Circuit Description SPI Timing Figure 6 SPI 8 bit read/write access with timing Figure 7 SPI 8 bit long address read/write access Version 0.2 Figure 8 SPI 16 bit long read/write access Preliminary Datasheet AX5043 ...
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... Figure 9 Wire-mode interface timing Version 0.2 PWRMODE register. AX5043 always drives DCLK. Transmit data must be applied to AX5043 synchronizes the RS232 signal to its internal are programmed via the serial peripheral interface (SPI). Preliminary 37 Circuit Description AX5043 using the AX5043 transmit and Datasheet AX5043 ...
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... Circuit Description General Purpose ADC (GPADC) The AX5043 features a general purpose ADC. The ADC input pins are GPADC1 and GPADC2. The ADC can be used either in differential (GPADC13) or single-ended mode (GPADC1 and GPADC2). To start a single conversion, write 1 to the BUSY bit in the BUSY bit to clear, or the GPADC Interrupt to be asserted ...
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... Note All addresses not documented here must not be accessed, neither in reading nor in writing. Note The retention column indicates if the register contents are preserved in power-down mode. Note To calculate the optimal settings use the AXSEM Version 0.2 Register Bank Description AX5043 configuration software. Preliminary 39 Datasheet AX5043 ...
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... Power Management Interrupt Mask IRQ Mask IRQ Mask RADIO EVENT – – MASK(8) Radio Event Mask Radio Event Mask IRQ Inversion IRQ Inversion IRQ Request IRQ Request RADIO EVENT – – REQ(8) Radio Event Request Radio Event Request Modulation Datasheet AX5043 ...
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... CLK Pin-state SYSCLK Pin Function DCLK Pin Function DATA Pin Function IRQ Pin Function ANTSEL Pin Function PWRAMP Pin Function – PWRAMP PWRAMP Control FIFO FIFO FULL EMPTY FIFO Control FIFO Data FIFO COUNT( – 8) Number of Words currently in FIFO Datasheet AX5043 41 ...
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... Synthesizer Frequency Synthesizer Frequency FLT(1:0) PLL Loop Filter Settings (Boosted) PLL Charge Pump Current PLL Auto-ranging Synthesizer Frequency Synthesizer Frequency Synthesizer Frequency Synthesizer Frequency Received Signal Strength Indicator Background RSSI ANT SEL DIV ENA Antenna Diversity Configuration Frequency Tracking Datasheet AX5043 ...
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... Wakeup Crystal Oscillator Early 2nd Frequency 2nd Frequency Decimation Factor Receiver Data-rate Receiver Data-rate Receiver Data-rate RXSI(1:0) Receiver Parameter Current Set FREQ SHAPE Modulator Configuration F FSK Frequency Deviation FSK Frequency Deviation FSK Frequency Deviation DIFF Modulator Configuration A Transmitter Bit-rate Datasheet AX5043 43 ...
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... Pattern Match Unit 0, Pattern Pattern Match Unit 0, Pattern Pattern Match Unit 0, Pattern Pattern Match Unit 0, Pattern Pattern Match Unit 0, Pattern Length Pattern Match Unit 0, Minimum Match Pattern Match Unit 0, Maximum Match Pattern Match Unit 1, Pattern Pattern Match Unit 1, Pattern Datasheet AX5043 ...
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... GPADC1 Value GPADC1 Value GPADC2VALUE(9:8) GPADC2 Value GPADC2 Value GPADC3VALUE(9:8) GPADC3 Value GPADC3 Value LPOSC LPOSC FAST ENA Low Power Oscillator Configuration Low Power Oscillator Calibration Filter Constant Low Power Oscillator Calibration Filter Constant Low Power Oscillator Calibration Reference Datasheet AX5043 45 ...
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... LPOSCPER(7:0) Version 0.2 – – – Preliminary Low Power Oscillator Calibration Reference Low Power Oscillator Calibration Frequency Low Power Oscillator Calibration – Frequency Low Power Oscillator Calibration Period Low Power Oscillator Calibration Period Datasheet AX5043 ...
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... 7.1. Typical Application Diagrams Using a Dipole Antenna and the internal TX/RX Switch Figure 10 Application diagram: Dipole antenna and internal TX/RX switch Version 0.2 Application Information Preliminary 47 Datasheet AX5043 ...
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... Application Information Using a single-ended Antenna and the internal TX/RX Switch Figure 11 Application diagram: Single-ended antenna and internal TX/RX switch Version 0.2 Preliminary Datasheet AX5043 ...
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... Using an external high-power PA and an external TX/RX Switch Figure 12 Application diagram: Single-ended antenna, external PA and external antenna switch Version 0.2 Application Information Preliminary 49 Datasheet AX5043 ...
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... Application Information Using the single-ended PA Figure 13 Application diagram: Single-ended antenna, single ended internal PA, without RX/TX Version 0.2 switch Preliminary Datasheet AX5043 ...
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... Using two Antenna Figure 14 Application diagram: Two single-ended antenna and external antenna switch Version 0.2 Application Information Preliminary 51 Datasheet AX5043 ...
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... Application Information Using an external VCO inductor Figure 15 Application diagram: External VCO inductor Version 0.2 Preliminary Datasheet AX5043 ...
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... Using an external VCO Figure 16 Application diagram: External VCO Version 0.2 Application Information Preliminary 53 Datasheet AX5043 ...
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... Application Information Using a TCXO Figure 17 Application diagram: Usage with TCXO Version 0.2 Preliminary Datasheet AX5043 ...
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... Package warp shall be 0.050 maximum 9. Leadframe material is copper A194 10. Coplanarity applies to the exposed pad as well as the terminal 11. YYWWXX is the packaging lot code 12. RoHS compliant Version 0.2 QFN28 Package Information AXSEM AX5043-1 YYWWXX Preliminary 55 Datasheet AX5043 ...
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... Version 0 25° to Peak Time Pb-Free Process 3 °C/sec max. T 150°C sMIN T 200°C sMAX t 60 – 180 sec min max. 25 ° to Peak T 217° – 150 sec L t 260° – 40 sec p 6°C/sec max. Preliminary Reflow Cooling Datasheet AX5043 ...
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... The fine pitch of the IC leads requires accurate alignment of the stencil and the printed circuit board. The stencil and printed circuit assembly should be aligned to within + 1 mil prior to application of the solder paste. 7. No-clean flux is recommended since flux from underneath the thermal pad will be difficult to clean if water-soluble flux is used. Version 0.2 QFN28 Package Information Preliminary 57 Datasheet AX5043 ...
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... QFN28 Package Information Figure 19: Solder paste application on exposed pad Minimum 50% coverage Version 0.2 62% coverage Figure 20: Solder paste application on pins Preliminary Maximum 80% coverage Datasheet AX5043 ...
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... AXSEM customers using or selling this product for use in such applications their own risk and agree to fully indemnify AXSEM for any damages resulting from such improper use or sale. Version 0.2 Life Support Applications Preliminary 59 Datasheet AX5043 ...
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... The copying, distribution and utilization of this document as well as the communication of its contents to others without expressed authorization is prohibited. Offenders will be held liable for the payment of damages. All rights reserved. Copyright © 2010 AXSEM AG Version 0.2 Phone +41 44 882 17 07 Fax +41 44 882 17 09 Email sales@axsem.com www.axsem.com Preliminary Datasheet AX5043 ...