STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 8

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5466
TIME DIVISION MULTIPLEXES (TDM)
8/130
Pin N°
Type
TTL
TTL
TTL
TTL
CMOS
CMOS
153
10
12
13
14
15
11
19
20
18
21
22
23
24
25
26
27
28
29
30
33
34
35
36
37
38
39
40
9
ft: five volts tolerant
I1_ft = Input TTL
I/O6 _ft = Input TTL/ Output TTL 6 mA
O3 _ft = Output TTL 3 mA O3T_ft = O3_ft+Tristate
O6D_ft = Output TTL 6mA, Open Drain
I/O8_fnt = Input TTL, /Output CMOS 8mA;
O4_fnt = Output CMOS 4mA
VCXO OUT
FRAMEA
FRAMEB
VCXO IN
CLOCKA
CLOCKB
Symbol
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
FSCV*
DCLK
FSCG
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
PSS
FS
O6DT_ft TDM0 Data Output 0
O6DT_ft TDM1 Data Output 1
O6DT_ft TDM2 Data Output 2
O6DT_ft TDM3 Data Output 3
O6DT_ft TDM4 Data Output 4
O6DT_ft TDM5 Data Output5
O6DT_ft TDM6 Data Output6
O6DT_ft TDM7 Data Output 7
O3_ft
O6_ft
O6_ft
O6_ft
O3_ft
Type
I3_ft
I3_ft
I3_ft
I3_ft
I3_ft
I3_ft
I3_ft
I3_ft
I3_ft
I3_ft
I3_ft
I3_ft
I3_ft
I3_ft
I3_ft
I3_ft
fnt: five volts not tolerant
I2_ft = I1_ft+pull up
VCXO input signal. This signal is compared to clock A(orB)
selected inside the Multi-HDLC .
VCXO error signal. This pin delivers the result of the comparison.
Input Clock A (4096kHz or 8192kHz)
Input Clock B (4096kHz or 8192kHz)
Clock A at 8kHz
Clock B at 8kHz
Data Clock issued from Input Clock A (or B). This clock is delivered by the cir-
cuit at 4096kHz (or 2048kHz). DOUT0/7 are transmitted on the rising edge of
this signal. DIN0/7 are sampled on the falling edge of this signal.
Frame synchronization for GCI at 8kHz.
This clock is issued from FRAME A (or B).
Frame synchronization for V Star at 8kHz
Frame synchronization.
This signal synchronizes DIN0/8 and DOUT0/7 and CB.
Programmable synchronization Signal.
PSS is programmed by the PS bit of connection memory.
TDM0 Data Input 0
TDM1 Data Input 1
TDM2 Data Input 2
TDM3 Data Input 3
TDM4 Data Input 4
TDM5 Data Input 5
TDM6 Data Input 6
TDM7 Data Input 7
TDM8 Data Input 8, Direct access to 1st 32 HDLC Controller
TDM9 Data Input 9, Direct access to 2nd 32 HDLC Controller
I3_ft = I1_ft+hysteresis
O6_ft = Output TTL 6mA
O6DT_ft = Output TTL 6mA, Open Drain or Tristate
O8T_fnt = Output CMOS
8mA
Function
I4_ft = I3_ft+pull up
I5_ft = I3_ft+pull down;
I/O8_fnt = Input TTL, /Output CMOS
8mA