MT48LC4M16A2TG-75 IT:G Micron Technology Inc, MT48LC4M16A2TG-75 IT:G Datasheet - Page 52
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MT48LC4M16A2TG-75 IT:G
Manufacturer Part Number
MT48LC4M16A2TG-75 IT:G
Description
DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M16A2TG-75_ITG.pdf
(72 pages)
Specifications of MT48LC4M16A2TG-75 IT:G
Density
64 Mb
Maximum Clock Rate
133 MHz
Package
54TSOP-II
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
6|5.4 ns
Operating Temperature
-40 to 85 °C
Organization
4Mx16
Address Bus
14b
Access Time (max)
6/5.4ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
140mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Not Compliant
Timing Diagrams
Figure 35:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
DQML, DQMH
COMMAND
A0–A9, A11
DQM /
BA0, BA1
CKE
A10
CLK
DQ
T = 100µs
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CLK stable
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MIN
DD
Initialize and Load Mode Register
and
t CKS
t CMS
Notes:
T0
NOP
t CKH
High-Z
t CMH
SINGLE BANK
t CMS
ALL BANKS
t CK
1. If CS# is HIGH at clock HIGH time, all commands applied are NOP.
2. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
BANKS
PRECHARGE
ALL
T1
t CMH
t RP
Precharge
all banks
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t CMS
Tn + 1
REFRESH
AUTO
t CMH
t CH
AUTO REFRESH
t RFC
NOP
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NOP
52
t CL
To + 1
REFRESH
AUTO
AUTO REFRESH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t RFC
NOP
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NOP
t AS
t AS
64Mb: x4, x8, x16 SDRAM
LOAD MODE
Tp + 1
REGISTER
CODE
CODE
t AH
t AH
Program Mode Register
©2000 Micron Technology, Inc. All rights reserved.
t MRD
Timing Diagrams
Tp + 2
NOP
2, 3, 4
Tp + 3
ACTIVE
BANK
ROW
ROW
DON’T CARE