CY2DP314OI Cypress Semiconductor Corp, CY2DP314OI Datasheet

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CY2DP314OI

Manufacturer Part Number
CY2DP314OI
Description
Manufacturer
Cypress Semiconductor Corp
Type
Clock Driverr
Datasheet

Specifications of CY2DP314OI

Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
1500MHz
Output Logic Level
ECL/PECL
Operating Supply Voltage (min)
-2.375/2.375V
Operating Supply Voltage (typ)
-2.5/-3.3/2.5/3.3V
Operating Supply Voltage (max)
-3.465/3.465V
Package Type
SSOP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Signal Type
ECL/HSTL/PECL
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Not Compliant
Cypress Semiconductor Corporation
Document #: 38-07550 Rev.*G
Features
• Four ECL/PECL differential outputs
• One ECL/PECL differential or single-ended inputs
• One HSTL differential or single-ended inputs (CLKB)
• Hot-swappable/-insertable
• 29 ps typical output-to-output skew
• 95 ps typical part-to-part skew
• 400 ps typical propagation delay
• 0.16 ps typical RMS phase jitter
• 7 ps typical peak period jitter
• 1.5-GHz operation (2.7-GHz maximum toggle
• PECL and HSTL mode supply range: V
• ECL mode supply range: V
• Industrial temperature range: –40°C to 85°C
• 20-pin SSOP package
• Temperature compensation like 100K ECL
Block Diagram
(CLKA)
frequency)
3.3V±5% with V
with V
CLK_SEL
CLKA#
CLKB#
CLKA
CLKB
VCC
CC
VCC
= 0V
VEE
VEE
VEE
EE
= 0V
E E
= –2.5V± 5% to –3.3V±5%
CC
1:4 Differential Clock/Data Fanout Buffer
= 2.5V± 5% to
198 Champion Court
Q0
Q0#
Q1
Q1#
Q2
Q2#
Q3
Q3#
Functional Description
The CY2DP314 is a low-skew, low propagation delay 2-to-4
differential fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications. The
device is implemented on SiGe technology and has a fully
differential internal architecture that is optimized to achieve
low signal skews at operating frequencies of up to 1.5 GHz (full
swing).
The device features two differential input paths that are multi-
plexed internally. This mux is controlled by the CLK_SEL pin.
The CY2DP314 may function not only as a differential clock
buffer but also as a signal-level translator and fanout on HSTL
or LVCMOS /LVTTL single-ended signal to four ECL/PECL
differential loads.
Since the CY2DP314 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2DP314 delivers consistent performance
over various platforms.
San Jose
CLK_SEL
Pin Configuration
CLKA#
CLKB#
CLKA
CLKB
VCC
VCC
VCC
VEE
NC
,
CA 95134-1709
20-pin SSOP
1
2
3
4
5
6
7
8
9
10
Revised August 22, 2005
20
19
18
17
16
15
14
13
12
11
VCC
Q0
Q0#
Q1
Q1#
Q2
Q2#
VCC
Q3
Q3#
CY2DP314
408-943-2600
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CY2DP314OI Summary of contents

Page 1

... VCC CLKB CLKB# VEE CLK_SEL VEE Cypress Semiconductor Corporation Document #: 38-07550 Rev.*G 1:4 Differential Clock/Data Fanout Buffer Functional Description The CY2DP314 is a low-skew, low propagation delay 2-to-4 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The ...

Page 2

Pin Definitions Pin Name I/O 1,10,11,20,3 VCC +PWR CLK_SEL I,PD 5 CLKA I,PD 6 CLKA# I, PD/PU 7 CLKB I,PD 8 CLKB# I, PD/PU [2] 9 VEE –PWR 18,16,14,12 Q[0:3]# O 19,17,15,13 Q[0:3] O Table 1. Control ...

Page 3

Absolute Maximum Ratings Parameter Description V Positive Supply Voltage CC V Negative Supply Voltage EE T Temperature, Storage S T Temperature, Junction J ESD ESD Protection h M Moisture Sensitivity Level SL Gate Count Total Number of Used Gates Multiple ...

Page 4

ECL DC Electrical Specifications Parameter Description V Negative Power Supply EE V ECL Input Differential cross point CMR [7] voltage V Output High Voltage OH V Output Low Voltage –3.3V ± –2.5V ± ...

Page 5

Timing Definitions Figure 1. PECL/ECL Input Waveform Definitions ...

Page 6

Test Configuration Standard test load using a differential pulse generator and differential measurement instrument ...

Page 7

Applications Information Termination Examples Figure 7. Standard LVPECL – PECL Output Termination Figure 8. Driving a PECL/ECL Single-ended Input ...

Page 8

... Figure 10. Termination for LVPECL to HTSL interface for VCC = 2.5V would use Ohms 2300 Ohms, and Z = 1000 Ohms. See application note titled PECL Translation, SAW Oscillators, and Specs Ordering Information Part Number CY2DP314OI CY2DP314OIT Lead-free CY2DP314OXI CY2DP314OXIT Document #: 38-07550 Rev.*G VDD-2 VCC ...

Page 9

... Document #: 38-07550 Rev.*G © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 10

Document History Page Document Title: CY2DP314 FastEdge SERIES 1:4 Differential Clock/Data Fanout Buffer Document Number: 38-07550 Orig. of REV. ECN NO. Issue Date Change ** 126779 06/13/03 RGL *A 128940 08/19/03 RGL *B 207710 See ECN RGL *C 237748 See ...

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