PCK111BD-F NXP Semiconductors, PCK111BD-F Datasheet - Page 3

• Manufacturer Part Number: PCK111BD-F
• Description: Clock Drivers & Distribution LO VOLT 1:1 DIFF PECL CLK DR
• Manufacturer: NXP Semiconductors
• Type: Clock Driverr

Specifications of PCK111BD-F

• Number Of Clock Inputs: 2
• Output Logic Level: ECL/PECL
• Mode Of Operation: Differential
• Output Frequency: 1500MHz
• Operating Supply Voltage (min): -2.25/2.25V
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Operating Supply Voltage (max): -3.8/3.8V
• Package Type: LQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: ECL/HSTL/PECL
• Mounting: Surface Mount
• Pin Count: 32
• Max Output Freq: 1500 MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Multiply / Divide Factor: 2:1
• Supply Voltage (max): +/- 3.8 V
• Supply Voltage (min): +/- 2.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: SOT-358
• Lead Free Status / RoHS Status: Not Compliant
• Other names: PCK111BD,128

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
1. To idle an unused differential clock input, connect one input terminal (e.g. CLK1) to V
Philips Semiconductors
Pin description
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
NOTE:
2004 Apr 23
SYMBOL
V
CLK_SEL
CLK0, CLK0
V
CLK1, CLK1
V
V
Q0–Q9
Q0–Q9
ESDCDM
SYMBOL
ESDHBM
SYMBOL
ESDMM
CC
BB
EE
CCO
Low voltage 1:10 differential
ECL/PECL/HSTL clock driver
(e.g. CLK1) open-circuit, in which case CLK1 will default LOW by its internal pull-down reistor. Inputs should not be shorted to ground or
V
V
T
V
V
V
CC
DIFF
amb
CC
CC
IR
.
Supply voltage
Electrostatic discharge (Human Body Model; 1.5 k , 100 pF)
Electrostatic discharge (Machine Model; 0 k , 200 pF)
Electrostatic discharge (Charge Device Model)
Supply voltage
Receiver input voltage
Input differential voltage
Operating ambient temperature range in free air
PIN
1
2
3, 4
5
6, 7
8
9, 16, 25, 32
31, 29, 27, 24,
22, 20, 18, 15,
13, 11
30, 28, 26, 23,
21, 19, 17, 14,
12, 10
DESCRIPTION
Supply voltage
Active CMOS clock select input
Differential ECL/PECL/HSTL
input pair
Reference voltage output
Differential ECL/PECL/HSTL
input pair
Ground
Output drive power supply
voltage
Differential PECL outputs
Differential PECL outputs
PARAMETER
1
PARAMETER
3
LOGIC SYMBOL
FUNCTION TABLE
V
CLK_SEL
(CLKinN)–
CONDITIONS
CLK0
CLK0
CLK1
CLK1
CLK_SEL
BB
V
and leave its complimentary input terminal
0
1
(CLKin)
Figure 3. Logic symbol
0
1
MIN
2.25
V
–40
—
EE
–0.5 to +4.6
V
LIMITS
>1000
BB
>1.75
>200
10
Active input
CLK0, CLK0
CLK1, CLK1
MAX
V
1.00
+85
3.8
CC
PCK111
SW00908
Product data
Q0:9
Q0:9
UNIT
UNIT
kV
V
V
V
V
V
V
C