UJA1061TW,512 NXP Semiconductors, UJA1061TW,512 Datasheet - Page 34

• Manufacturer Part Number: UJA1061TW,512
• Manufacturer: NXP Semiconductors

Specifications of UJA1061TW,512

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 8.
[1]
Table 9.
UJA1061_6
Product data sheet
Bit
3
2
1 and 0
Bit
15 and 14
13
12
11
10
9
8
7
6
V2D will be set when V2 is reactivated after a failure. See
System Diagnosis register bit description
Interrupt Enable register and Interrupt Enable Feedback register bit description
Symbol
V2D
V1D
CANMD
[1:0]
Symbol
A1, A0
RRS
RO
WTIE
OTIE
GSIE
SPIFIE
-
VFIE
6.13.6 Interrupt Enable register and Interrupt Enable Feedback register
These registers allow setting, clearing and reading back the interrupt enable bits of the
SBC.
Description
V2 diagnosis
V1 diagnosis
CAN Mode Diagnosis
Description
register address
Read Register Select
Read Only
Watchdog Time-out
Interrupt Enable
Over-Temperature
Interrupt Enable
Ground Shift Interrupt
Enable
SPI clock count Failure
Interrupt Enable
reserved
Voltage Failure Interrupt
Enable
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[1]
Rev. 06 — 9 March 2010
Value
1
0
1
0
10
01
00
Value
01
0
0
1
0
1
0
1
0
1
0
0
1
0
11
1
1
Section
…continued
6.6.2.2.
Function
OK
fail; V2 is disabled due to an overload situation
OK; V1 always above V
fail; V1 was below V
again with read access
CAN is in Active mode
CAN is in On-line mode
CAN is in On-line Listen mode
CAN is in Off-line mode, or V2 is not active
Function
select the Interrupt Enable register
read the Interrupt register
read the Interrupt Enable Feedback register
read the register selected by RRS without writing to
Interrupt Enable register
read the register selected by RRS and write to Interrupt
Enable register
a watchdog overflow during Standby causes an interrupt
instead of a reset event (interrupt based cyclic wake-up
feature)
no interrupt forced on watchdog overflow; a reset is forced
instead
exceeding or dropping below the temperature warning limit
causes an interrupt
no interrupt forced
exceeding or dropping below the GND shift limit causes an
interrupt
no interrupt forced
wrong number of CLK cycles (more than, or less than 16)
forces an interrupt; from Start-up mode and Restart mode a
reset is performed instead of an interrupt
no interrupt forced; SPI access is ignored if the number of
cycles does not equal 16
should always be set to logic 0
clearing of V1D, V2D or V3D forces an interrupt
no interrupt forced
Fault-tolerant CAN/LIN fail-safe system basis chip
[1]
UV(VFI)
UV(VFI)
since last read access; bit is set
since last read access
UJA1061
© NXP B.V. 2010. All rights reserved.
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