KSZ8993MLI Micrel Inc, KSZ8993MLI Datasheet - Page 59

2+1 Port 10/100 Switch W/Tranceivers & Frame Buffers, 128-Ld PQFP( , I-Temp)

KSZ8993MLI

Manufacturer Part Number
KSZ8993MLI
Description
2+1 Port 10/100 Switch W/Tranceivers & Frame Buffers, 128-Ld PQFP( , I-Temp)
Manufacturer
Micrel Inc
Datasheet

Specifications of KSZ8993MLI

Number Of Primary Switch Ports
3
Internal Memory Buffer Size
32
Fiber Support
Yes
Integrated Led Drivers
Yes
Package Type
PQFP
Data Rate (typ)
10/100Mbps
Vlan Support
Yes
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Pin Count
128
Mounting
Surface Mount
Jtag Support
No
Operating Supply Voltage (max)
1.89/3.465V
Operating Supply Voltage (min)
1.71/3.135V
Power Dissipation
800mW
Operating Temperature Classification
Industrial
Data Rate
100Mbps
Lead Free Status / RoHS Status
Supplier Unconfirmed
Other names
576-3350

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KSZ8993MLI
Manufacturer:
Micrel Inc
Quantity:
10 000
Part Number:
KSZ8993MLI
Manufacturer:
MICREL/麦瑞
Quantity:
20 000
Register 25 (0x19): Port 1 Control 9
Register 41 (0x29): Port 2 Control 9
Register 57 (0x39): Port 3 Control 9
Bit
7-0
Register 26 (0x1A): Port 1 Control 10
Register 42 (0x2A): Port 2 Control 10
Register 58 (0x3A): Port 3 Control 10
Bit
7-4
3-0
Register 27 (0x1B): Port 1 Control 11
Register 43 (0x2B): Port 2 Control 11
Register 59 (0x3B): Port 3 Control 11
Bit
7
6
5
4
Micrel, Inc.
October 2008
Receive low
priority rate
control [7:0]
Receive low
priority rate
control [11:8]
Receive high
priority rate
control [11:8]
Receive
differential
priority rate
control
Low priority
receive rate
control enable
High priority
receive rate
control enable
Low priority
receive rate
flow control
enable
Name
Name
Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
This register along with port control 10, bits [7:4]
form a 12-bits field to determine how many
“32Kbps” low priority blocks can be received (in a
unit of 4Kbytes in a one second period).
Description
These bits along with port control 9, bits [7:0]
form a 12-bits field to determine how many
“32Kbps” low priority blocks can be received (in a
unit of 4Kbytes in a one second period).
These bits along with port control 8, bits [7:0]
form a 12-bits field to determine how many
“32Kbps” high priority blocks can be received (in
a unit of 4Kbytes in a one second period).
Description
= 1, If bit 6 is also ‘1’ this will enable receive rate
control for this port on low priority packets at the
low priority rate. If bit 5 is also ‘1’, this will enable
receive rate control on high priority packets at the
high priority rate.
= 0, receive rate control will be based on the low
priority rate for all packets on this port.
= 1, enable port’s low priority receive rate control
feature
= 0, disable port’s low priority receive rate control
= 1, If bit 7 is also ‘1’ this will enable the port’s
high priority receive rate control feature. If bit 7 is
a ‘0’ and bit 6 is a ‘1’, all receive packets on this
port will be rate controlled at the low priority rate.
= 0, disable port’s high priority receive rate
control feature
= 1, flow control may be asserted if the port’s low
priority receive rate is exceeded.
= 0, flow control is not asserted if the port’s low
priority receive rate is exceeded.
59
Default
0x00
Default
0x0
0x0
Default
0
0
0
0
M9999-020606
KSZ8993M/ML

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