TFRA84J131BL-3-DB LSI, TFRA84J131BL-3-DB Datasheet - Page 20

• Manufacturer Part Number: TFRA84J131BL-3-DB
• Manufacturer: LSI

Specifications of TFRA84J131BL-3-DB

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

TFRA84J13 Ultraframer
DS3/E3/DS2/E2/DS1/E1/DS0
2.5 Pin Definitions
This section describes the function of each of the device pins. Pin functionality is descriptive information. The actual
functionality is dependent upon the device configuration via the registers.
Table 2-4. LVDS Framer Reference Clock
Table 2-5. DS3/E3 Out
Table 2-6. DS3/E3 In
20
20
* Optional: selected by MPU/top-level register UMPR_LVDS_REF_SEL. External reference voltage can be sourced from a low-impedance resistor
AB6, AD3, AD2
AC5, AB8, AB5
AJ1, AC4, AC3
AD1, AB2, W3
(<1 k ) divider circuit decoupled with a 0.1 F capacitor.
AH1, AA6, V2
Y4, AC1, V1
V3, V4, AB1
AN4
AG9
AP4
AK6
AL5
AL6
AJ6
Pin
Pin
Pin
DS3NEGDATAOUT[3:1]
DS3POSDATAOUT[3:1]
DS3DATAOUTCLK[3:1]
DS3NEGDATAIN[3:1]
DS3POSDATAIN[3:1]
DS3DATAINCLK[3:1]
DS3RXCLKOUT[3:1]
CTAPTH
Symbol
Symbol
THSCP
THSCN
RESLO
REF10
REF14
Symbol
RESHI
*
*
Type
Type
Type
I pd DS3/E3 Data Output Clock. 44.736 MHz or 34.368 MHz clock input
I pd
I pd
I pd
L
—
—
O
O
O
IN
I
I
Framer High-Speed Clock. The clock on this pin is internally routed
to the DS1/E1 framers and is used as an internal master clock. This
input clock can be at 155 MHz or 622 MHz. Note there are no advan-
tages in using a 622 MHz clock vs. a 155 MHz clock.
Center Tap TH. LVDS buffer terminator center tap for THSCP/N. An
optional 0.1 µF capacitor, connected between CTAP pin and ground,
will improve the common-mode rejection of the LVDS input buffers.
Resistor. A 100 , 1% resistor is required between the RESHI and
RESLO pins as a reference for the LVDS input buffer termination.
Reference 1.0 V. External 1 V reference voltage pin (optional).
Reference 1.4 V. External 1.4 V reference voltage pin (optional).
DS3/E3 Positive Data Output. Either contains the positive-rail of the
B3ZS/HDB3 encoded output data, or single-rail NRZ data.
DS3/E3 Negative Data Output. Negative-rail B3ZS/HDB3 encoded
output data. Not used in single-rail mode (held low in this case).
and is typically connected to a crystal oscillator or clocking chip.
This clock is required for M13 and E13 applications.
DS3/E3 Receive Clock Output. 44.736 MHz DS3/34.368 MHz E3
clock out to external circuit.
DS3/E3 Positive Data Input. Either contains the positive-rail of the
B3ZS/HDB3 encoded input data, or single-rail NRZ data.
DS3/E3 Negative Data Input. Either contains the negative-rail of the
B3ZS/HDB3 encoded input data, or in single-rail mode, this input may
be used to count bipolar violations.
DS3/E3 Data Input Clock. 44.736 MHz or 34.368 MHz clock for the
DS3/E3 positive and negative data inputs.
Hardware Design Guide, Revision 5
Name/Description
Name/Description
Name/Description
Agere Systems Inc.
July 13, 2004