CY7C924ADX-AC Cypress Semiconductor Corp, CY7C924ADX-AC Datasheet - Page 36

• Manufacturer Part Number: CY7C924ADX-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AC

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
and may be tied either HIGH or LOW. To place the
CY7C924ADX into synchronous modes, FIFOBYP* must be
LOW.
This mode is usually used for products that must meet specific
predefined protocol requirements, and cannot tolerate the
uncontrolled insertion of C5.0 fill characters. The host system
is required to asset TXEN* and to provide new data at every
appropriate rising edge of REFCLK to maintain the data
stream. If TXEN* is not asserted, the Encoder is loaded with
C5.0 (K28.5) sync characters. Because the Encoder is
enabled, the transmitted C5.0 characters follow all 8B/10B
encoding rules.
Input Register Mapping
In Encoded modes, the bits of the TXDATA input bus are
mapped into characters (as shown in
including a TXSVS bit, eight or ten bits of data, and a TXSC/D*
bit to select either Special Character codes or Data characters.
If the TXSVS bit is HIGH, an SVS (C0.7) character is passed
to the encoder, regardless of the contents of the other TXDATA
inputs. If the TXSVS bit is LOW, the associated TXDATA
character is encoded per the remaining bits in that character.
The TXSC/D* bit controls the encoding of the TXDATA[7:0] or
TXDATA[9:0] bits of each character. It is used to identify if the
input character represents a Data Character or a Special
Character code. If TXSC/D* is LOW, the character is encoded
using the Data Character codes listed in
If TXSC/D* is HIGH, the character is encoded using the
Special Character codes listed in
Synchronous Pre-encoded
In synchronous pre-encoded mode (FIFOBYP* and ENCBYP*
are LOW), both the Transmit FIFO and the 8B/10B encoder
are bypassed, and data passes directly from the Transmit
Input Register to the Serializer. The Serializer operates
synchronous to REFCLK to generate the serial data bit-clock.
As selected by SPDSEL and RANGESEL, the REFCLK input
is multiplied by 5 or 10 when BYTE8/10* is HIGH or by 6 or 12
when BYTE8/10* is LOW. In this mode the TXINT, TXHALT*,
TXSVS and TXSOC inputs are used as part of the data input
bus.
This mode is usually used for products containing external
encoders or scramblers, that must meet specific protocol
requirements. The host system is required to assert TXEN*
and to provide new data at every appropriate rising edge of the
REFCLK to maintain the data stream. If TXEN* is not asserted,
the Serializer is loaded with C5.0 (K28.5) sync characters.
However, because the bypassed encoder is not able to track
the running disparity of the previously transmitted character,
the transmitted C5.0 characters may be received with a
running disparity code-rule violation.
In this mode the LSB of each input character (TXDATA[0]) is
shifted out first, followed sequentially by TXDATA[1] through
TXDATA[9].
Asynchronous Encoded
Asynchronous Encoded mode is the most powerful operating
mode of the CY7C924ADX. Both the Transmit FIFO and the
Encoder are enabled (FIFOBYP* and ENCBYP* are HIGH).
This allows transmission of normal data streams, while
Table 12 on page
Table 1 on page
Table 11 on page
55.
13),
51.
offering the added benefits of embedded cell or packet
markers, an expanded command set, serial addressing, and
in-band bypass-signaling (for flow control or other purposes).
All characters added to the data stream to support these
additional capabilities may be automatically extracted by the
Receive Control State Machine in the CY7C924ADX Receiver.
The Serializer operates synchronous to REFCLK, which is
multiplied by 2.5, 5, or 10 to generate the serial data bit-clock
(as selected by SPDSEL and RANGESEL). In this mode the
TXSOC, TXSC_D*, TXRST*, TXSVS, TXINT/TXDATA[8],
TXHALT*/TXDATA[9], and TXSTOP* inputs are interpreted.
Embedded Cell Marker
An embedded cell marker is used to mark the start of cells or
frames of information passed from one end of the link to the
other. This marker is set by asserting TXSOC HIGH, with
TXSC/D* and TXSVS both LOW, along with the remaining
data on the TXDATA bus. When the data character accompa-
nying this marker is read from the output end of the Transmit
FIFO, a C8.0 (K23.7) character is inserted into the data stream
prior to the associated data character being read from the
Transmit FIFO.
Expanded Commands
The standard 8B/10B Character set contains all 256 possible
data characters, but only twelve special or command
characters. To allow use of a larger selection of command
codes, a Special Character code was selected to expand the
command set.
An expanded command marker is used to mark the associated
data as any one of 256 (2
marker is generated by asserting both TXSOC and TXSC/D*
HIGH, with TXSVS being LOW, along with the associated data
on the TXDATA bus. When the character accompanying this
marker is read from the output end of the Transmit FIFO, a
C9.0 (K27.7) character is inserted into the data stream prior to
the data character being read from the Transmit FIFO.
Serial Addressing
The CY7C924ADX receiver has the ability to accept or reject
data based on an internal address-controlled switch. This
switch is turned on when a serial address matching the
receiver address settings is received. When the serial address
received does not match the address programmed into the
receiver, the receiver’s input is ignored.
A serial address is transmitted by asserting TXSOC, TXSC/D*,
and TXSVS all HIGH. When the character accompanying this
marker is read from the output end of the Transmit FIFO, a
C10.0 (K29.7) character is inserted into the data stream prior
to the data characters being read from the Transmit FIFO. The
serial address is either 8 or 10 bits depending on the level on
BYTE8/10*.
In-Band Bypass-Signaling
In-band bypass-signaling allows a signal to be sent to the
remote receiver without that signal having to pass through the
Transmit (or Receive) FIFO. When TXINT transitions, a
character is immediately inserted in the data stream at the
Encoder block, delaying other data encoding for a cycle.
When TXINT transitions from 0→1, a C0.0 (K28.0) special
character is sent. When TXINT transitions from 1→0, a C3.0
8
) possible commands codes. This
CY7C924ADX
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