CY7C9335A-270AC Cypress Semiconductor Corp, CY7C9335A-270AC Datasheet

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CY7C9335A-270AC

Manufacturer Part Number
CY7C9335A-270AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C9335A-270AC

Frame Format Support
DVB/SMPTE
Number Of Transceivers
10
Data Rate
270Mbps
Operating Supply Voltage (typ)
5V
Screening Level
Commercial
Pin Count
100
Mounting
Surface Mount
Package Type
TQFP
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temperature (min)
0C
Operating Temperature (max)
70C
Lead Free Status / RoHS Status
Not Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C9335A-270AC
Manufacturer:
CY
Quantity:
71
Cypress Semiconductor Corporation
Document #: 38-02083 Rev. **
Features
Functional Description
SMPTE-259M Operation
The CY7C9335A is a CMOS integrated circuit designed to
decode SMPTE-125M bit-parallel digital characters (or other
data formats) using the SMPTE-259M decoding rules.
Following decoding, the characters are framed by locating the
30-bit TRS pattern in the parallel character stream. The
framed characters are then output.
• Fully compatible with SMPTE-259M
• Fully compatible with DVB-ASI
• Operates from a single +5V supply
• 100-pin TQFP package
• Decodes 10-bit parallel digital streams for 27M
• Operates with CY7B9334 SMPTE HOTLink deseri-
• X
Logic Block Diagram
characters/sec (270 Mbits/sec serial)
alizer/receiver
be bypassed for raw data output
9
SYNC_EN
D
+ X
BYPASS
DVB_EN
D
0
9
(SC/D)
(RVS)
CKR
4
OE
+ 1 descrambler and NRZI-to-NRZ decoder may
D
D
D
D
D
D
D
D
8
7
6
5
4
3
2
1
11
10
3901 North First Street
10
19
4
Descrambler/Framer-Controller
The inputs of the CY7C9335A are designed to be directly
mated to a CY7B9334 HOTLink receiver, which converts the
SMPTE-259M compatible high-speed serial data stream into
10-bit parallel characters.
This device performs both TRS (sync) detection and framing,
data descrambling with the SMPTE-259M X
and NRZI-to-NRZ decoding. These functions operate at a 27
MHz character rate. For those systems operating with
non-SMPTE-259M compliant video streams (or for diagnostic
purposes), the descrambler and NRZI decoding functions can
be disabled.
DVB-ASI Operation
The CY7C9335A also contains the necessary multiplexers,
control inputs and outputs, to control a DVB-ASI-compliant
video stream. DVB-ASI operation is enabled through
activation of a single input signal. This allows a single
serial-to-parallel input port to support both SMPTE and DVB
data streams under software or hardware control.
In DVB-ASI mode the CY7C9335A automatically enables both
the 8B/10B decoder and multibyte framer present in the
CY7B9334 receiver/deserializer. All error detection, fill, and
command codes are detected and output by the CY7C9335A.
The CY7C9335A operates from a single +5V supply. It is
available in a 100-pin TQFP space saving package.
10
SMPTE-259M/DVB-ASI
San Jose
10
,
CA 95134
Revised October 13, 2003
CY7C9335A
9
+X
408-943-2600
RF
A/B
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
H_SYNC
SYNC_ERR
4
+1 algorithm,
9
8
7
6
5
4
3
2
1
0
(SVS)
(SC/D)
[+] Feedback

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CY7C9335A-270AC Summary of contents

Page 1

... In DVB-ASI mode the CY7C9335A automatically enables both the 8B/10B decoder and multibyte framer present in the CY7B9334 receiver/deserializer. All error detection, fill, and command codes are detected and output by the CY7C9335A. The CY7C9335A operates from a single +5V supply available in a 100-pin TQFP space saving package ...

Page 2

... CY7B9334 Port Select. When in DVB-ASI mode, this output will alternately select either the INA± or INB± receiver port based on errors detected in the data stream. This allows CY7C9335A to operate with normal and inverted DVB-ASI data streams (as would be commonly found on DVB-ASI streams routed through SMPTE switches). This requires the CY7B9334 INA± ...

Page 3

... DVB Mode Enable. This signal is sampled by the rising edge of the CKR clock. If DVB_EN is active (LOW), the data present on the D CKR Input Recovered Clock Read. This clock controls all synchronous operations of the CY7C9335A. It operates at the character rate which is equivalent to one tenth the deserialized bit-rate. This clock is driven directly by the CKR output of the CY7B9334 deserializer. OE Input Output Enable ...

Page 4

... CY7B9334 if it exceeds a preset statistical error rate. For this to operate the A/B output of the CY7C9335A needs to be connected to the A/B input of the CY7B9334 SMPTE HOTLink receiver (through the appropriate resistive divider). If the CY7C9335A is not used for DVB-ASI operation, the A/B output may be left open. CY7C9335A or CC bits in the output register ...

Page 5

... Note 2 GND GND Output Disabled O CC [3, Max 0.5V CC OUT Test Conditions MHz 5.0V CC 238 5V 5.0V OUTPUT GND 5 pF 170 INCLUDING JIG AND SCOPE (b) CY7C9335A 0.5V to +7.0V 2001 V 200 mA Ambient Temperature + Min. Max. Unit 2.4 V 0.5 V 2.0 7.0 V 0 160 mA Max. Unit ...

Page 6

... The clock period may be extended 90% for a single clock cycle when framing occurs in DVB-ASI mode. 7. Test load (b) used for this parameter. Test load (a) used for all other AC parameters. Document #: 38-02083 Rev. ** [5] Description [6] [7] t CKR CPRL Package Type 100-pin Thin Quad Flat Pack CY7C9335A Min. Max. Unit 14.5 14 CPRH t PD DVB_EN RF Operating Range Commercial ...

Page 7

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C9335A 51-85048-B ...

Page 8

... Document History Page Document Title: CY7C9335A SMPTE-259M/DVB-ASI Descrambler/Framer-Controller Document Number: 38-02083 REV. ECN NO. Issue Date ** 129112 12/09/03 Document #: 38-02083 Rev. ** Orig. of Change Description of Change LAR Pin-to-pin compatible with CY7C9335 CY7C9335A Page [+] Feedback ...

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