CY7C9335A-270AC Cypress Semiconductor Corp, CY7C9335A-270AC Datasheet - Page 3

• Manufacturer Part Number: CY7C9335A-270AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9335A-270AC

• Frame Format Support: DVB/SMPTE
• Number Of Transceivers: 10
• Data Rate: 270Mbps
• Operating Supply Voltage (typ): 5V
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02083 Rev. **
Pin Descriptions
SYNC_EN
SYNC_ERR Output
PD
PD
PD
D
D
D
DVB_EN
CKR
OE
V
V
CC
SS
9
8 1
0
(RVS)
(SC/D)
9
8 1
0
Name
(RVS)
(SC/D)
Input
Output
Output
Output
Input
Input
Input
Input
Input
Input
I/O
CY7C9335A SMPTE-259M Decoder (continued)
Sync Filtering Enabled. This input controls the operation of the SMPTE framer. When this signal is
active (HIGH) and a TRS sequence is detected, if the 10-bit character boundary is different from the
previously received TRS, the H_SYNC output is toggled, but the character offset is not updated. If the
immediately following TRS also has a different offset, the H_SYNC output is again toggled and the
character offset is updated to match that of the detected TRS sequence. When this signal is inactive
(LOW), the framer will update the character offset and toggle H_SYNC on every detected TRS sequence.
Sync Error. This output pulses HIGH for one CKR clock period when a TRS sequence is detected that
is offset from its previous 10-bit character offset. This pulse starts at the same time as the H_SYNC signal
toggles, but only occurs when SYNC_EN is active (HIGH) and the character offset is not updated.
Parallel Data 9 or Received Violation Symbol. This is the MSB of the framed output data bus. It is
latched in the output register at the rising edge of CKR. When DVB_EN is active (LOW), this output
indicates that the character present on PD
When DVB_EN is disabled (HIGH), the character in the output register bits PD
framed character of the SMPTE data stream.
Parallel Data 8 through 1. The signals present at the PD
at the rising edge of CKR. When DVB_EN is disabled (HIGH), these signals are the middle eight bits of
the descrambled and framed SMPTE 10-bit data character. When DVB_EN is active (LOW), these
signals are full DVB-ASI data bus.
Parallel Data 0 or Special Code/Data Select. This is the LSB of the output data field. It is latched in the
output register at the rising edge of CKR. When DVB_EN is active (LOW), this output identifies that the
character present in PD
inactive (HIGH), this output data bit is the LSB of the descrambled and framed SMPTE data character.
Input Bit 9. This is the MSB of the input register. It should be connected directly to the CY7B9334
deserializer output signal RVS(Q
Input Bits 8 through 1. These signals should be connected directly to the CY7B9334 deserializer output
signals Q
Input Bit 0. This is the LSB of the input register. It should be connected directly to the CY7B9334
deserializer output signal SC/D(Q
DVB Mode Enable. This signal is sampled by the rising edge of the CKR clock. If DVB_EN is active
(LOW), the data present on the D
Recovered Clock Read. This clock controls all synchronous operations of the CY7C9335A. It operates
at the character rate which is equivalent to one tenth the deserialized bit-rate. This clock is driven directly
by the CKR output of the CY7B9334 deserializer.
Output Enable. When this signal is HIGH all outputs are driven to their normal logic levels. When LOW,
all outputs are placed in a High-Z state.
Power.
Ground.
7 0
respectively.
8 1
is either a command (HIGH) or data (LOW) character). When DVB_EN is
j
).
0 9
a
).
inputs are latched and routed to the PD
8 0
identifies the type of error detected in the character stream.
Description
8 1
outputs are latched in the output register
0 9
9 0
outputs.
is a descrambled and
CY7C9335A
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