LU82541PI Intel, LU82541PI Datasheet
LU82541PI
Specifications of LU82541PI
Available stocks
Related parts for LU82541PI
LU82541PI Summary of contents
Page 1
... Restriction on Hazardous Substances (RoHS)-banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales represen- tative Datasheet Host Off-Loading — ...
Page 2
... Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...
Page 3
Contents 1.0 Introduction......................................................................................................................... 7 1.1 Document Scope................................................................................................... 7 1.2 Reference Documents...........................................................................................8 1.3 Product Codes....................................................................................................... 8 2.0 Architectural Overview .....................................................................................................11 2.1 External Architecture Block Diagram...................................................................11 2.2 Internal MAC Architecture Block Diagram...........................................................12 2.3 Integrated 10/100/1000Mbps PHY ......................................................................12 2.4 System Interface .................................................................................................12 3.0 ...
Page 4
Networking Silicon 5.4 Visual Pin Assignments....................................................................................... 46 Figures 1 82541(PI/GI/EI) External Architecture Block Diagram ........................................ 11 2 Internal Architecture Block Diagram.................................................................... Test Loads for General Output Pins.............................................................. Test Loads for General Output ...
Page 5
Serial EEPROM Interface Signals.......................................................................37 22 Serial FLASH Interface Signals...........................................................................37 23 LED Signals.........................................................................................................37 24 Other Signals.......................................................................................................38 25 IEEE Test Signals ...............................................................................................38 26 PHY Signals ........................................................................................................38 27 Test Interface Signals..........................................................................................38 28 Digital Power Signals ..........................................................................................38 29 Analog Power Signals .........................................................................................39 30 ...
Page 6
Networking Silicon Note: This page is intentionally blank. vi ...
Page 7
... Local Area Network (LAN). With SMB, management packets can be routed to or from a management processor. The SMB port enables industry standards, such as Intelligent Platform Management Interface (IPMI) and Alert Standard Forum (ASF) 2. implemented using the 82541(PI/GI/EI) ...
Page 8
... PCI Mobile Design Guide, Revision 1.1. PCI Special Interest Group (SIG). Software driver developers should contact their local Intel representatives for programming information. 1.3 Product Codes The product ordering codes for the 82541 Family of Gigabit Ethernet Controllers: • GD82541PI • GD82541GI • GD82541EI • LU82541PI • LU82541GI • LU82541EI 8 ...
Page 9
Architectural Overview 2.1 External Architecture Block Diagram The 82541(PI/GI/EI) architecture is a derivative of the 82542, 82543, and 82544 designs that provided Media Access Controller (MAC) functionality as well as an integrated 10/100/1000Mbps copper PHY. The 82541(PI/GI/EI) family architecture ...
Page 10
Networking Silicon 2.2 Internal MAC Architecture Block Diagram Figure 2 shows the major internal function blocks of 82541(PI/GI/EI) MAC device. Compared to its predecessors, the 82541(PI/GI/EI) MAC adds improved receive-packet filtering to support SMBus-based manageability, as well as ...
Page 11
Signal Descriptions 3.1 Signal Type Definitions The signals of the 82541(PI/GI/EI) controller are electrically defined as follows: Name I Input. Standard input only digital signal. O Output. Standard output only digital signal. TS Tri-state. Bi-directional tri-state digital input/output signal. ...
Page 12
Networking Silicon 3.2.1 PCI Address, Data and Control Signals (44) Symbol Type AD[31:0] TS C/BE#[3:0] TS PAR TS FRAME# STS IRDY# STS TRDY# STS STOP# STS 12 Name and Function Address and Data. Address and data signals are ...
Page 13
Symbol Type IDSEL I DEVSEL# STS VIO P 3.2.2 Arbitration Signals (2) Symbol Type REQ# TS GNT# I 3.2.3 Interrupt Signal (1) Symbol Type INTA# TS 3.2.4 System Signals (4) Symbol Type CLK I M66EN I RST# I I/O CLK_RUN# ...
Page 14
Networking Silicon 3.2.5 Error Reporting Signals (2) Symbol Type SERR# OD PERR# STS 3.2.6 Power Management Signals (3) Symbol Type LAN_ I PWR_GOOD PME# OD AUX_PWR I 3.2.7 SMB Signals (3) Symbol Type TS SMBCLK OD TS SMBDATA ...
Page 15
EEPROM and Serial FLASH Interface Signals (9) Symbol Type EEMODE I EEDI O EEDO I EECS O EESK O FLSH_CE# O FLSH_SCK O FLSH_SI O FLSH_SO/ I LAN_DISABLE# 3.4 Miscellaneous Signals 3.4.1 LED Signals (4) Symbol LED0 / LINK_UP# ...
Page 16
Networking Silicon 3.4.2 Other Signals (4) Symbol Type SDP[3:0] TS PHY Signals 3.5 3.5.1 Crystal Signals (2) Symbol Type XTAL1 I XTAL2 O Note: The 82541 clock input circuit is optimized for use with an external crystal. However, ...
Page 17
MDI[3]+/- A IEEE_TEST- A IEEE_TEST+ A 3.6 Test Interface Signals (6) Symbol TEST JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST# 3.7 Power Supply Connections 3.7.1 Digital and Analog Supplies Symbol Type 3.3V P ANALOG_1.8V P CLKR_1.8V P XTAL_1.8V P 1.2V P ANALOG_1.2V ...
Page 18
... Reserved Ground. This pin is reserved by Intel and may have factory test functions. For normal operation, connect to ground. Reserved No connect. This pin is reserved by Intel and may have factory test functions. For normal operation, do not connect any circuit to these pins. Do not connect pull-up or pull-down resistors. ...
Page 19
Voltage, Temperature, and Timing Specifications 4.1 Absolute Maximum Ratings Table 1. Absolute Maximum Ratings Symbol DC supply voltage on 3.3 V pins VDD (3.3) with respect to VSS DC supply voltage on 1.8 V pins VDD (1.8) with respect ...
Page 20
Networking Silicon Table 2. Recommended Operating Conditions (Sheet Symbol tr/tf input rise/fall time (Schmitt input) Operating temperature range T A (ambient) T Junction temperature J a. Sustained operation of the device at conditions exceeding these ...
Page 21
Table 4. 1.8V Supply Voltage Ramp Output Capacitance range when using PNP circuit Capacitance Input Capacitance range when using PNP circuit Capacitance Capacitance Equivalent series resistance of output ESR capacitance Ictrl_18 Maximum output current rating to CTRL18 a. Tantalum capacitors ...
Page 22
Networking Silicon 4.3 DC Specifications Table 6. DC Characteristics Symbol Parameter DC supply voltage on 3.3 V VDD (3.3) pins DC supply voltage on 1.8 V VDD (1.8) pins DC supply voltage on 1.2 V VDD (1.2) pins ...
Page 23
Table 8. Power Specifications - D3cold unplugged link Typ Icc Max Icc b (mA) (mA Total Device Power ...
Page 24
Networking Silicon Table 10. Power Specifications - Complete Subsystem Complete Subsystem (Reference Design) Including Magnetics, LED, Regulator Circuits D3cold - wake disabled Typ Max Icc Icc a (mA) (mA 1.2 ...
Page 25
Table 11. I/O Characteristics (Sheet (Continued) Symbol Parameter Output high IOH current: Output high voltage: VOH 3.3 V PCI Output low voltage: VOL 3.3 V PCI Off-state output IOZ leakage current Output short IOS circuit current Input ...
Page 26
Networking Silicon Table 13. 25 MHz Clock Input Requirements Symbol Cin Input capacitance T Operating temperature Aptp Input clock amplitude (peak-to-peak) Vcm Clock common mode a. Clock jitter is defined according to the recommendations of part 40.6.1.2.5 IEEE ...
Page 27
AC Test Loads for General Output Pins Symbol CL TDO CL PME#, SDP[3:0] CL EEDI, EESK CL LED[3:0] Figure 3. AC Test Loads for General Output Pins 4.5 Timing Specifications Table 17. PCI Bus Interface Clock Parameters Symbol TCYC CLK ...
Page 28
Networking Silicon Figure 4. AC Test Loads for General Output Pins 3.3 V Clock 0.5 Vcc 0.4 Vcc 0.3 Vcc Table 18. PCI Bus Interface Timing Parameters Symbol CLK to signal valid delay: bussed TVAL signals CLK to ...
Page 29
Figure 5. AC Test Loads for General Output Pins CLK Output Delay Tri-State Output Figure 6. AC Test Loads for General Output Pins CLK V TH Input V TL Table 19. PCI Bus Interface Timing Measurement Conditions Symbol VTH Input ...
Page 30
Networking Silicon Figure 7. TVAL (max) Rising Edge Test Load Figure 8. TVAL (max) Falling Edge Test Load Figure 9. TVAL (min) Test Load 30 Pin 1/2 inch max. 25Ω Pin 1/2 inch max. 25Ω 10 ...
Page 31
Figure 10. TVAL Test Load (PCI 5 V Signaling Environment) Pin NOTE load used for maximum times. Minimum times are specified with 0 pF load. Table 20. Link Interface Rise and Fall Times Symbol Parameter TR Clock rise ...
Page 32
Networking Silicon Table 21. EEPROM Link Interface Clock Requirements Symbol Microwire EESK pulse width TPW SPI EESK pulse width a. The EEPROM clock is derived from a 125 MHz internal clock. Table 22. EEPROM Link Interface Clock Requirements ...
Page 33
Package and Pinout Information This section describes the 82541(PI/GI/EI) device physical characteristics. The pin number-to- signal mapping is indicated beginning with 5.1 Package Information The 82541(PI/GI/EI) device is a 196-lead plastic ball grid array (BGA) measuring ...
Page 34
Networking Silicon Figure 12. 196 PBGA Package Pad Detail As illustrated in Figure copper area is 0.60 mm and the opening in the solder mask is 0.45 mm. The nominal ball sphere diameter is 0.50 mm. 34 Detail ...
Page 35
Thermal Specifications The 82541(PI/GI/EI) device is specified for operation when the ambient temperature (T ° the range (case temperature) is calculated using the equation (θ ...
Page 36
Networking Silicon 5.3 Pinout Information Table 14. PCI Address, Data and Control Signals Signal AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] Table 15. PCI Arbitration Signals Signal REQ# GNT# ...
Page 37
Table 18. Error Reporting Signals Signal Pin SERR# A2 Table 19. Power Management Signals Signal PME# LAN_PWR_GOOD Table 20. SMB Signals Signal Pin SMBCLK A10 Table 21. Serial EEPROM Interface Signals Signal Pin EESK M10 EEDO N10 Table 22. Serial ...
Page 38
Networking Silicon Table 24. Other Signals Signal SDP[0] N14 SDP[1] P13 Table 25. IEEE Test Signals Signal IEEE_TEST- Table 26. PHY Signals Signal MDI[0]- C14 MDI[0]+ C13 MDI[1]- E14 MDI[1]+ E13 Table 27. Test Interface Signals Signal JTAG_TCK ...
Page 39
Table 28. Digital Power Signals (Sheet (Continued) Signal Pin 3.3V P2 3.3V P12 Table 29. Analog Power Signals Signal Pin ANALOG_1.2V E11 ANALOG_1.2V E12 ANALOG_1.2V G13 ANALOG_1.2V H11 Table 30. Grounds and No Connect Signals Signal Pin ...
Page 40
Networking Silicon Table 32. Signal Names in Pin Order (Sheet Signal Name NC SERR# 3.3V IDSEL AD[25] PME# 3.3V AD[30] LAN_PWR_GOOD SMBCLK 3.3V LED0 / LINK_UP# TEST NC AD[22] AD[23] VSS AD[24] AD[26] AD[27] VSS ...
Page 41
Table 32. Signal Names in Pin Order (Sheet (Continued) Signal Name AD[28] AD[29] CLK_RUN# SMBDATA VSS LED1 / ACTIVITY# AVSS MDI[0]+ MDI[0]- AD[18] AD[19] AD[20] RSVD_VSS VSS VSS VSS VSS NC NC ANALOG_1.8V CLKR_1.8V AVSS IEEE_TEST- 3.3V ...
Page 42
Networking Silicon Table 32. Signal Names in Pin Order (Sheet (Continued) Signal Name MDI[1]+ MDI[1]- IRDY# FRAME# C/BE#[2] VSS VSS VSS VSS VSS VSS VSS AVSS RSVD_NC MDI[2]+ MDI[2]- CLK VIO TRDY# PLL_1.2V 1.2V 1.2V ...
Page 43
Table 32. Signal Names in Pin Order (Sheet (Continued) Signal Name 1.2V 1.2V 1.2V VSS VSS ANALOG_1.2V NC MDI[3]+ MDI[3]- PAR PERR# GNT# EEMODE 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V AUX_PWR XTAL_1.8V XTAL2 AD[16] VSS 3.3V ...
Page 44
Networking Silicon Table 32. Signal Names in Pin Order (Sheet (Continued) Signal Name 3.3V XTAL1 AD[14] AD[15] C/BE#[1] 1.2V 1.2V VSS RSVD_NC NC 1.2V 1.2V VSS JTAG_TMS JTAG_TRST# JTAG_TCK AD[11] AD[12] AD[13] C/BE#[0] AD[5] VSS ...
Page 45
Table 32. Signal Names in Pin Order (Sheet (Continued) Signal Name 3.3V AD[0] 3.3V FLSH_SCK EEDO RSVD_NC VSS SDP[2] SDP[0] NC 3.3V AD[8] AD[6] AD[3] AD[2] EECS VSS FLSH_SO EEDI CTRL12 3.3V SDP[1] NC Networking Silicon — ...
Page 46
Networking Silicon 5.4 Visual Pin Assignments AD[22] AD[21] AD[18] 2 SERR# AD[23] M66EN AD[19] 3 3.3V VSS REQ# AD[20] RSVD_ C/BE#[3] 4 IDSEL AD[24] VSS RSVD_ 5 AD[25] AD[26] VSS NC 6 ...