TS68C429AVF E2V, TS68C429AVF Datasheet

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Features • 8 Independent Receivers (Rx) • 3 Independent Transmitters (Tx) • Full TS68K Family Microprocessor Interface Compatibility • 16-bit Data-bus • ARINC 429 Interface: “1” and “0” Lines, RZ Code • Support all ARINC 429 Data Rate Transfer and ...

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Hardware Overview TS68C429A 2 The TS68C429A is a high performance ARINC 429 controller designed to interface pri- mary to the TS68K family microprocessor in a straight forward fashion (see Atmel “Application Notes” on page 33). It can be connected to ...

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Figure 1. Simplified Block Diagram 2120A–HIREL–08/02 TS68C429A 3 ...

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Package Figure 1. Signal Description Pin Name Type A0-8 I D0-15 I LDS I UDS I R/W I DTACK O IRQTX O IACKTX I IEITX I IEOTX O IRQRX O IACKRX I IEIRX I IEORX I TX1H O ...

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Figure 1. Signal Description (Continued) Pin Name Type RX2L I RX3H I RX3L I RX4H I RX4L I RX5H I RX5L I RX6H I RX6L I RX7H I RX7L I RX8H I RX8L I RESET I V /GND I CC ...

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Figure 2. Functional Signal Groups Diagram Scope Applicable Documents MIL-STD-883 Requirements General TS68C429A 6 Figure 2 illustrates the functional signal groups. This drawing describes the specified requirements for the ARINC multi channel receiver/transmitter, in compliance either with MIL-STD-863 class B ...

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Design and Construction Terminal Connections Package Special Recommended Conditions for CMOS Devices Electrical Characteristics Table 1. Absolute Maximum Ratings Symbol Parameter V Supply Voltage CC V Input Voltage I P Max Power Dissipation dmax T Operating Temperature case T Storage ...

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Unless otherwise stated, all voltages are referenced to the reference terminal. Table 2. Recommended Condition of Use Symbol Parameter V Supply Voltage CC V Low Level Input Voltage IL V High Level Input Voltage IH T Operating Temperature case C ...

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Power Considerations Mechanical and Environment Marking 2120A–HIREL–08/02 The average chip-junction temperature, T ⋅ θ ° Ambient Temperature θ = Package Thermal Resistance, Junction-to-Ambient ...

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Quality Conformance Inspection DESC/MIL-STD-883 Electrical Characteristics General Requirements Table 4. DC Electrical Characteristics C ≤ T ≤ +125 ° ° With - -40 case Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Output ...

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Clock Timing Table 6. Clock System (CLK SYS) Symbol Parameter t S Clock Period cyc Clock Pulse Width CLS CHS Rise and Fall Times crS cfS Table 7. Clock ARINC (CLK ARINC) Symbol Parameter ...

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Figure 5. Write Cycle 3. LDS/UDS can be asserted on the same or previous CLK-SYS period as CS but (3) and (4) must be met. Figure 6. Interrupt Cycle (IEIxx = 0) Notes UDS = 1, D15-D8 stay ...

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Figure 7. Interrupt Cycle (IEIxx = 1) Notes UDS = 1, D15-D8 stay hi-z else D15-D8 drive the bus with a stable unknown value IEOxx goes low, neither vector nor DTACK are generated, else IEOxx stays ...

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Table 8. Timing Characteristic (Continued) Number Symbol Parameter LDS/UDS high to R/W invalid SHRWI 19 t DTACK low to data in hold time DKLDIH CS or LDS/UDS or IACKxx high data out hold 20 t SHDOH ...

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To detect the end of the message, the Gap-Controller waits for a Gap after the last received bit so, at each CLK ARINC cycle, a counter is incremented and com- pared to the content of the Gap-Register ...

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Figure 9. Receiver Channel Block Diagram Note: A valid message is stored in the Shift-Reg. until a new message arrives and so may be transferred to the message buffer as soon as the buffer is “freed”. TS68C429A 16 2120A–HIREL–08/02 ...

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Figure 10. Rebuilt clock CLK-ARINC Gap register Synchro counter End of msg Register Description 2120A–HIREL–08/02 Four registers are associated to each receiver channel. These four registers are: a) receiver control b) gap register c) message buffer d) label control matrix ...

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Figure 11. USD access Test mode Channel enable Table 9. Register Control Register Description Bit Function Bit 15 Channel enable Bit 14 Test mode ...

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Table 9. Register Control Register Description Bit Function Bit 5 Not used Bit 4 Not used Bit Channel priority: order Figure 12. Gap Register Description 2120A–HIREL–08/02 Comments The lowest value will give the highest priority. Each channel ...

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Figure 13. Label Control Matrix Figure 14. Transmitter Channel Unit (TCU) Overview Outputs TS68C429A 20 The TCU is composed of three ARINC transmit channels and has per channel: • a parallel to serial converter to translate the messages into two ...

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Figure 15. Transmitter Channel Unit Outputs Description 2120A–HIREL–08/02 The block diagram of a transmit channel is given is given in Figure 16. Only the third channel can be switched to internal lines for test mode, otherwise the channels are iden- ...

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Figure 16. Transmitter Channel Block Diagram Register Description TS68C429A 22 Three registers are associated to each transmitter channel: • the frequency register, • the transmitter control register, • the FIFO. • The Frequency Register The frequency register is only accessible ...

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Figure 18. Transmitter Control Register Table 10. Transmission Control Register Description Bit Function Bit 15 Enable transmission Bit 14 Test (only 3rd channel) Bit Not used Bus 11 Parity control Bit 10 Parity control Bit 9 to ...

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General Circuit Control Logical Control Unit (LCU) Figure 19. Status Register TS68C429A 24 • FIFO The FIFO is seen as two 16-bit words. The Most Significant Word (MSW) must be writ- ten first. The Least Significant Word (LSW) write increments ...

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Table 11. Description of LCU Status Register Bit Function Bit 15, 13, 11 FIFO channel empty Bit 14, 12, 10 End of transmission on channel Bit 8 RX wrong parity. This feature is available ...

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Figure 21. Write Cycle Flow Chart Interrupt Control Unit (ICU) TS68C429A 26 • Daisy Chain The ICU is composed of 2 interrupt blocks with a daisy chain capability (transmitter and receiver blocks). The daisy chain allows more than one circuit ...

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Figure 22. Interrupt Control Unit Daisy Chain Use 2120A–HIREL–08/02 • Vectored Interrupt They are 15 possibilities to generate an interrupt and two lines to handle them more efficient, a unique vector number for each cause is given to ...

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TS68C429A 28 • Register Description Any internal status change that induces a bit to be set in the status-register will generate an interrupt if this cause is enabled by the Mask-register and if no highest priority cause is already activated ...

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Figure 26. Self-test Description 2120A–HIREL–08/02 Figure 25. Base Register • The Interrupt Vector Number During an interrupt acknowledge cycle, an 8-bit vector number is presented to the micro- processor on D0-D7 lines. This vector number corresponds to the interrupt source ...

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Register Description TS68C429A 30 Figure 27. Self-test Register The self-test register can be split in three parts: 1. bit 0: Used to enable receiver wrong parity detection. This bit has been imple- mented to guarantee compatibility with previous designs: 0: ...

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Self-test Use Memory MAP Address 2120A–HIREL–08/02 1: Self-test fail. bit 13: Result of Transmitter 3 self-test: 0: (if bit 10 is set to 1) self-test pass, 1: Self-test fail. bit 14: 0: ...

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Memory MAP (Continued) Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH ...

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Application Notes Microprocessor Interface Figure 28. Typical Interface with TS68000 (*) This kind of application can also work with an independant clk 2120A–HIREL–08/02 (for additional details order the AN 68C429A) TS68C429A 33 ...

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Figure 29. Typical Interface with 68020/CPU 32 Core Microcontrollers TS68C429A 34 2120A–HIREL–08/02 ...

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Figure 30. Typical Interface with 68302 In this example, receiver interrupts have a higher priority than transmitter interrupts. 2120A–HIREL–08/02 TS68C429A 35 ...

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Programs Flow-chart Figure 31. Initialization after Reset Flow-chart TS68C429A 36 2120A–HIREL–08/02 ...

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Figure 32. Receiver without Interrupt Flow-chart Figure 33. Receiver with Interrupt Flow-chart TS68C429A IT START Read "MSW" Read "LSW" IT END 37 ...

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TS68C429A 38 Figure 34. Transmitter without Interrupt Flow-chart Figure 35. Transmitter with Interrupt Flow-chart 2120A–HIREL–08/02 ...

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Preparation for Delivery Packaging Certificate of Compliance Handling 2120A–HIREL–08/02 Figure 36. First FIFO Access Microcircuits are prepared for delivery in accordance with MIL-I-38535 or DESC. Atmel offers a certificate of compliance with each shipment of parts, affirming the prod- ucts ...

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Package Mechanical Data PGA 84 CQFP 132 TS68C429A 40 2120A–HIREL–08/02 ...

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Terminal Connections 84-lead PGA Assignment 132-lead CQFP Assignment 2120A–HIREL–08/02 TS68C429A 41 ...

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... Ordering Information Standard Product Atmel Part Number Norms TS68C429AMR Atmel Standard TS68C429AMF Atmel Standard TS68C429AVR Atmel Standard TS68C429AVF Atmel Standard HI-REL Products Atmel Part Number Norms TS68C429AMRB/C MIL-STD-883 TS68C429AMFB/C MIL-STD-883 TS68C429ADESCxx DESC TS68C429ADESCxx DESC Part number Temperature range: M: -55°C/+125°C V: -40° ...

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Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem ...