DJLXT905LC.C2 831645 Intel, DJLXT905LC.C2 831645 Datasheet - Page 31

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DJLXT905LC.C2 831645

Manufacturer Part Number
DJLXT905LC.C2 831645
Description
Manufacturer
Intel
Datasheet

Specifications of DJLXT905LC.C2 831645

Lead Free Status / RoHS Status
Not Compliant
TPIP/TPIN
4.3
Datasheet
Document Number: 249271
Revision Number: 004
Revision Date: 19-Oct-2005
NOTE:
RCLK
1. RSD changes at the rising edge of RCLK. Mode 3 samples the controller at the falling edge.
NOTE:
1. RXD changes at the rising edge of RCLK. Mode 3 samples the controller at the falling edge.
RXD
TPIP/TPIN
CD
Figure 19. Mode 3 RCLK/Start-of-Frame Timing
Figure 20. Mode 3 RCLK/End-of-Frame Timing
RCLK
RXD
Generated from TCLK
CD
Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low)
Timing diagrams for Mode 3 include
1
1
t
CD
0
0
1
1
t
t
RD
SWS
0
1
0
t
DATA
1
0
1
0
1
0
1
Recovered Clock
LXT905 Universal 10BASE-T Transceiver with 3.3V Support
0
1
0
1
0
1
Figure 19
0
0
t
1
1
RDS
1
t
CDOFF
Recovered from Input Data Stream
1
0
through
0
0
1
0
1
0
Figure
t
RDH
0
1
t
SWE
22.
0
0
0
1
Generated from TCLK
1
0
0
1
1
1
1
0
31
1

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