DJLXT971ALE.A4 Cortina Systems Inc, DJLXT971ALE.A4 Datasheet - Page 84

• Manufacturer Part Number: DJLXT971ALE.A4
• Manufacturer: Cortina Systems Inc

Specifications of DJLXT971ALE.A4

• Lead Free Status / RoHS Status: Not Compliant

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
Table 52
Table 53
Cortina Systems
Auto-Negotiation Expansion - Address 6, Hex 6
Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7
®
1. RO = Read Only LH = Latching High
1. RO = Read Only. R/W = Read/Write
6.15:6
7.10:0
7.15
7.14
7.13
7.12
7.11
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Bit
6.5
6.4
6.3
6.2
6.1
6.0
Bit
Reserved
Base Page
Parallel
Detection Fault
Link Partner Next
Page Able
Next Page Able
Page Received
Link Partner A/N Able
Next Page (NP)
Reserved
Message Page (MP)
Acknowledge 2
(ACK2)
Toggle (T)
Message/
Unformatted Code
Field
Name
Name
Ignore when read.
This bit indicates the status of the auto-negotiation
variable base page. It flags synchronization with
the auto-negotiation state diagram, allowing
detection of interrupted links. This bit is used only
if register bit 16.1 (that is, Alternate NP feature) is
set.
0 = Base page = False (base page not received)
1 = Base page = True (base page received)
0 = Parallel detection fault has not occurred.
1 = Parallel detection fault has occurred.
0 = Link partner is not next page able.
1 = Link partner is next page able.
0 = Local device is not next page able.
1 = Local device is next page able.
This bit is cleared on Read. If register bit 16.1 is
set, the Page Received bit is also cleared when
either mr_page_rx = false or transmit_disable =
true.
1 = Indicates a new page is received and the
0 = Link partner is not auto-negotiation able.
1 = Link partner is auto-negotiation able.
0 = Last page
1 = Additional next pages follow
Ignore when read.
0 = register bits 7.10:0 are user defined.
1 = register bits 7.10.0 follow IEEE message page
0 = Cannot comply with message
1 = Complies with message
0 = Previous value of the transmitted Link Code
1 = Previous value of the transmitted Link Code
If register bits 7.13 = 0, register bits 7.10:0 are
user-defined.
If register bits 7.13 = 1, register bits 7.10:0 follow
IEEE message page format.
received code word is loaded into Register 5
(Base Pages) or Register 8 (Next Pages) as
specified in Clause 28 of IEEE 802.3.
format.
Word equalled logic one
Word equalled logic zero
Description
Description
8.0 Register Definitions - IEEE
Type
RO/LH
RO/LH
RO/LH
Type
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
1
1
Base Registers
Default
Default
0000
0000
001
Page 84
0
0
0
0
1
0
0
0
0
1
0
0