WJLXT901ALC.A4 865818 Intel, WJLXT901ALC.A4 865818 Datasheet
WJLXT901ALC.A4 865818
Specifications of WJLXT901ALC.A4 865818
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WJLXT901ALC.A4 865818 Summary of contents
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... Full-Duplex Capable (20 Mbps) Diagnostic Features Four LED Drivers AUI/RJ-45 Loopback Remote Signaling of Link-Down and Jabber conditions For technical assistance on this product, please call 1-800-628-8686, or send an e-mail to support@mailbox.intel.com. Datasheet Telecom Backplane USB to Ethernet Converters Convenience Features Automatic/Manual AUI/RJ-45 Selection Automatic Polarity Correction ...
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... Information in this document is provided in connection with Intel property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...
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Contents 1.0 Pin Assignments and Signal Descriptions .................................................................... 8 2.0 Functional Description .................................................................................................. 11 2.1 Controller Compatibility Modes ........................................................................... 12 2.2 Transmit Function................................................................................................ 12 2.2.1 Jabber Control Function ......................................................................... 13 2.2.2 SQE Function ......................................................................................... 13 2.2.2.1 SQE Disable Function (LXT907 ...
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Contents Figures 1 LXT901/907 Block Diagram .................................................................................. 7 2 LXT901/907 Pin Assignments ............................................................................... 8 3 LXT901/907 TPO Output Waveform .................................................................. 12 4 Jabber Control Function ..................................................................................... 13 5 SQE Function ..................................................................................................... 14 6 Collision Detection Function ............................................................................... 16 7 Link ...
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Tables 1 LXT901/907 Signal Descriptions ........................................................................... 9 2 Controller Compatibility Modes ........................................................................... 12 3 Crystal Specifications .......................................................................................... 20 4 Suitable Crystals ................................................................................................. 20 5 Suitable Magnetics .............................................................................................. 21 6 Absolute Maximum Ratings................................................................................. 31 7 Recommended Operating Conditions ................................................................. 31 8 ...
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Contents Revision History Date June 2001 6 Revision Page # 20 Table 3: Changed Nom frequency from “25.0” to “20.0.” 23 Added 0.1 F label to capacitor at bottom of Figure 9 graphic. Added 0.1 F label to capacitor at ...
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Figure 1. LXT901/907 Block Diagram AUTOSEL MODE SELECT LOGIC Controller Compatibility PAUI Port Select LBK Loopback LI Link test TCLK CLKI XTAL OSC CLKO MANCHESTER TEN ENCODER TXD RLD REMOTE SIGNALING RJAB RCMPT SQUELCH / LINK CD DETECT LEDL RXD ...
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LXT901/907 — Universal 10BASE-T and AUI Transceivers 1.0 Pin Assignments and Signal Descriptions Figure 2. LXT901/907 Pin Assignments RLD JAB 9 TEST 10 TCLK 11 TXD 12 TEN 13 Part # LXT901/907PC XX CLKO 14 LOT # ...
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... LI = Low Jabber Indicator. Output goes High to indicate Jabber state. I Test. For Intel internal use only recommended to tie this pin High externally. Transmit Clock MHz clock output. This clock signal should be directly connected to the transmit clock input of the controller. Transmit Data. Input signal containing NRZ data to be transmitted on the I network ...
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LXT901/907 — Universal 10BASE-T and AUI Transceivers Table 1. LXT901/907 Signal Descriptions (Continued) PLCC LQFP Symbol I/O LEDC FDE 22 38 LBK 23 39 GND1 33 55 GND2 – 40 GNDA 24 42 RBIAS 25 44 RCMPT ...
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... I/O Column Coding Input Output Open Drain 2.0 Functional Description The LXT901/907 Universal 10BASE-T and AUI Transceivers perform the physical layer signaling (PLS) and Media Attachment Unit (MAU) functions as defined by the IEEE 802.3 specification. They function as PLS-only devices (for use with 10BASE-2 or 10BASE-5 coaxial cable networks Integrated PLS/MAU devices (for use with 10BASE-T twisted-pair networks) ...
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... Controller Compatibility Modes The LXT901/907 ia compatible with most industry standard controllers, including devices produced by Motorola, AMD, Intel, Fujitsu, National Semiconductor, Seeq, and Texas Instruments. Four different control signal timing and polarity schemes (Modes 1 through 4) are required to achieve this compatibility. Mode select pins (MD0 and MD1) determine controller compatibility ...
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Jabber Control Function Figure state diagram of the LXT901/907 Jabber control function. The on-chip watchdog timer prevents the DTE from locking into a continuous transmit mode. When a transmission exceeds the time limit, the watchdog timer ...
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... Manchester decoder, then output as decoded NRZ data and receive timing on the RXD and RCLK pins, respectively. An internal RC filter and an intelligent squelch function discriminate noise from link test pulses and valid data streams. The receive function is activated only by valid data streams above the squelch level and with proper timing ...
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Polarity Reverse Function The LXT901/907 polarity reverse function uses both link pulses and End-of-Frame data to determine the polarity of the received signal. If Link Integrity Testing is disabled, polarity detection is based only on received data. A reversed ...
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LXT901/907 — Universal 10BASE-T and AUI Transceivers Figure 6. Collision Detection Function DO=Active TPI=Idle XMIT=Enable Output TPO=DO DI=DO DO=Active TPI=Active XMIT=Enable A DO=Idle+ XMIT=Disable DO=Active TPI=Idle 2.4 Loopback Functions 2.4.1 Standard Twisted-Pair Loopback The LXT901/907 provides the standard loopback function ...
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Forced Twisted-Pair Loopback “Forced” twisted-pair loopback is controlled by the LBK pin. When the twisted-pair port is selected and LBK is High, twisted-pair loopback is “forced”, overriding collisions on the twisted- pair circuit. When LBK is Low, normal loopback ...
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LXT901/907 — Universal 10BASE-T and AUI Transceivers Figure 7. Link Integrity Test Function Power On Idle Test Start_Link_Loss_Timer Start_Link_Test_Min_Timer Link_Loss_Timer_Done TPI=Idle Link_Test_Rcvd=False Link Test Fail Reset Link_Count=0 XMIT=Disable RCVR=Disable LPBK=Disable TPI=Active Link_Test_Rcvd=False TPI=Idle Link Test Fail Extended XMIT=Disable RCVR=Disable LPBK=Disable ...
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Remote Signaling The LXT901/907 transmits standard link pulses which meet the IEEE 802.3 10BASE-T specification. However, the LXT901/907 encodes additional status information into the link pulse by varying the link pulse timing. This is referred to as remote signaling. ...
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LXT901/907 — Universal 10BASE-T and AUI Transceivers The LXT901 is designed with an STP Select pin that allows the device to match both 100 and 150 media. A dual resistor combination can be configured to accommodate either line termination, as ...
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Magnetics Information The LXT901 and LXT907 require a 1:1 ratio for the receive transformer and a 1: transmit transformer on the twisted-pair interface. The AUI Interface requires a 1:1 ratio for both the transmit and receive transformers. Designers should ...
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LXT901/907 — Universal 10BASE-T and AUI Transceivers Programmable option pins are grouped center left. The PAUI pin is tied Low and all other option pins are tied High. This set-up selects the following options: • Automatic Port Selection (PAUI Low ...
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Figure 9. LAN Adapter Board - Auto Port Select with External LPBK Control 20 pF TXD TXE TXC NS8390 BACK-END RXC CONTROLLER RXD INTERFACE CRS COL LOOPBACK LBK ENABLE PROGRAMMING OPTIONS REMOTE STATUS LINE STATUS 330 330 330 330 Green ...
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LXT901/907 — Universal 10BASE-T and AUI Transceivers 3.4.2 Full-Duplex Support Figure 10 shows the LXT907 with a Texas Instruments 380C24 CommProcessor. The 380C24 is compatible with Mode 4 (MD0 and MD1 both High). When used with the 380C24 or other ...
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Dual Network Support - 10Base-T and Token Ring Figure 11 shows the LXT901/907 with a Texas Instruments 380C26 CommProcessor. The 380C26 is compatible with Mode 4 (MD0 and MD1 both High). When used with the 380C26, both the LXT901/907 ...
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LXT901/907 — Universal 10BASE-T and AUI Transceivers 3.4.4 Manual Port Select with Link Test Function With MD0 tied Low and MD1 tied High, the LXT901/907 logic and framing are set to Mode 3 (compatible with Fujitsu MB86950 and MB86960, and ...
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Figure 13. Manual Port Select with Seeq 8005 Controller External 20 MHz Source CLKI CLKI LPBK LBK CSN CD 8005 RxD RXD RxC RCLK COLL COL TxEN TEN TCLK TxC TXD TxD PAUI Port Selection AUTOSEL NTH MD0 MD1 DSQE ...
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... Three Media Application Figure 14 shows the LXT907 in Mode 2 (compatible with Intel 82596 controllers) with additional media options for the AUI port. Two transformers are used to couple the AUI port to either a D- connector or a BNC connector. (A DP8392 coax transceiver with PM6044 power supply is required to drive the thin coax network through the BNC ...
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AUI Encoder/Decoder ONLY In Figure 15, the DTE is connected to a coaxial network through the AUI. AUTOSEL is tied Low and PAUI is tied High, manually selecting the AUI port. The twisted-pair port is not used. With MD1 ...
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... RJ-45 connector. (The AUI port is not used). With MD0 tied High and MD1 tied Low, the LXT901 logic and framing are set to Mode 2 (compatible with Intel 82596 controllers MHz system clock input at CLK1 is used in place of the crystal oscillator. (CLK0 is left open) ...
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... LXT901/907. These specifications are guaranteed by test except where noted “by design.” Minimum and maximum values listed in operating conditions specified in For all Quality and Reliability issues (for example, parts packaging and thermal specifications), please send your questions to Intel at the following e-mail address: qr.requests@intel.com. Table 6. Absolute Maximum Ratings Parameter ...
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LXT901/907 — Universal 10BASE-T and AUI Transceivers Table 8. I/O Electrical Characteristics (Continued) Parameter Output rise time TCLK & RCLK Output fall time TCLK & RCLK CLKI rise time (externally driven) CLKI duty cycle (externally driven) Normal Mode Supply current ...
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Table 10. Twisted-Pair Electrical Characteristics (Continued) Parameter Receive input impedance Normal Threshold; NTH = Differential High Squelch Reduced Threshold Threshold; NTH = Low 1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are ...
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LXT901/907 — Universal 10BASE-T and AUI Transceivers Table 13. RCLK/End-of-Frame Timing Parameter RCLK after CD off Rcv data throughput delay 2 CD turn off delay Receive block out after TEN off RCLK switching delay after CD off (LXT907 only; Mode ...
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Timing Diagrams for Mode 1 (MD1 = Low, MD0 = Low) Figures Figure 17. Mode 1 RCLK/Start-of-Frame Timing TPIP/TPIN or DIP/DIN RCLK t DATA RXD Figure 18. Mode 1 ...
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LXT901/907 — Universal 10BASE-T and AUI Transceivers Figure 19. Mode 1 Transmit Timing TEN t EHCH TCLK TXD TPO Figure 20. Mode 1 Collision Detect Timing CI t COLD COL Figure 21. Mode 1 COL/CI Output Timing TEN COL Figure ...
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Timing Diagrams for Mode 2 (MD1=Low, MD0=High) Figures Figure 23. Mode 2 RCLK/Start-of-Frame Timing TPIP/TPIN or DIP/DIN RCLK t DATA RXD NOTE: 1. RXD changes at the rising ...
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LXT901/907 — Universal 10BASE-T and AUI Transceivers Figure 25. Mode 2 Transmit Timing TEN TCLK TXD TPO Figure 26. Mode 2 Collision Detect Timing CI t COLD COL Figure 27. Mode 2 COL/CI Output Timing TEN COL Figure 28. Mode ...
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Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low) Figures Figure 29. Mode 3 RCLK/Start-of-Frame Timing (LXT901 only TPIP/TPIN or DIP/DIN RCLK t DATA RXD NOTE: 1. ...
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LXT901/907 — Universal 10BASE-T and AUI Transceivers Figure 31. Mode 3 RCLK/Start-of-Frame Timing (LXT907 only TPIP/TPIN or DIP/DIN SWS RCLK Generated from TCLK RXD NOTE: 1. RXD changes at the rising edge ...
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Figure 33. Mode 3 Transmit Timing TEN t EHCH TCLK TXD TPO Figure 34. Mode 3 Collision Detect Timing CI t COLD COL Figure 35. Mode 3 COL/CI Output Timing TEN COL NOTE: 1. RXD changes at the rising edge ...
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LXT901/907 — Universal 10BASE-T and AUI Transceivers 4.4 Timing Diagrams for Mode 4 (MD1 = High, MD0 = High) Figures Figure 37. Mode 4 RCLK/Start-of-Frame Timing TPIP/TPIN or DIP/DIN ...
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Figure 39. Mode 4 Transmit Timing TEN TCLK TXD TPO Figure 40. Mode 4 Collision Detect Timing CI t COLD COL Figure 41. Mode 4 COL/CI Output Timing TEN COL Figure 42. Mode 4 Loopback Timing LBK t KHEH TEN ...
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LXT901/907 — Universal 10BASE-T and AUI Transceivers 5.0 Mechanical Specifications Figure 43. LXT901/907 Package Specifications 44-Pin PLCC • Part Number LXT901PC and LXT907PC • Commercial Temp Range ( Inches ...
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... HSBGA (BGA with heat slug) xxxx = 3-5 Digit Alphanumeric Product Code IXA Product Prefix = PHY layer device LXT = Switching engine IXE = Formatting device (MAC) IXF = Network processor IXP Intel Package Designator DJ = LQFP FA = TQFP FL = PBGA (<1.0 mm pitch PBGA (1.27 mm pitch QFP with heat spreader HD ...
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