WJLXT901ALC.A4 865818 Intel, WJLXT901ALC.A4 865818 Datasheet - Page 37

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WJLXT901ALC.A4 865818

Manufacturer Part Number
WJLXT901ALC.A4 865818
Description
Manufacturer
Intel
Datasheet

Specifications of WJLXT901ALC.A4 865818

Lead Free Status / RoHS Status
Compliant
4.2
Datasheet
Document #: 249097
Revision #: 002
Rev. Date: June 19, 2001
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
TPIP/TPIN
or DIP/DIN
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
or DIP/DIN
TPIP/TPIN
Figure 23. Mode 2 RCLK/Start-of-Frame Timing
Figure 24. Mode 2 RCLK/End-of-Frame Timing
RCLK
RXD
CD
RCLK
RXD
CD
Timing Diagrams for Mode 2 (MD1=Low, MD0=High)
Figures 23 - 28
1
1
t
CD
0
0
1
1
t
0
RD
0
t
1
DATA
1
1
0
0
0
1
1
1
Universal 10BASE-T and AUI Transceivers — LXT901/907
0
0
0
1
1
0
t
0
1
RDS
1
t
1
1
CDOFF
0
0
0
1
1
0
0
t
RDH
0
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
37

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