CY7C9689A-AI Cypress Semiconductor Corp, CY7C9689A-AI Datasheet

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... FIFOs may also be bypassed (disabled) to create a reference-locked serial transmission link. For those systems requiring even greater FIFO storage capability, external FIFOs may be directly coupled to the CY7C9689A through the parallel interface without the need for additional glue-logic. The TTL parallel I/O interface may be configured as either a FIFO (configurable for depth expansion through external FIFOs pipeline register extender ...

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... Control 4B/5B, 5B/6B Decoder State Machine Transmit Deserializer Control Framer State Machine Receive Clock/Data Recovery Bit Clock Routing Matrix INA OUTB CURSETB CURSETA CY7C9689A RXCLK 13 Mode CONTROL CE TXEN RXEN MUX TXHALT TXRST RXRST RFEN TXBISTEN RXBISTEN RESET MODE RANGESEL SPDSEL RXMODE[1:0] ...

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... VLTN 6 TXBISTEN 7 RXCLK 8 TXHALT 9 RXFULL REFCLK TXRST TXEN 18 RXHALF 19 TXSC/D 20 RXEMPTY 21 TXDATA[0] 22 RXDATA[11]/RXCMD[1] 23 RXMODE[1] 24 RXMODE[ Document #: 38-02020 Rev CY7C9689A CY7C9689A SPDSEL 74 RANGESEL 73 RFEN 72 TXFULL TXHALF 69 RXEN 68 TXCLK 67 RXRST RXSC RXDATA[0] 60 TXEMPTY 59 RXDATA[1] 58 TXCMD[ TXCMD[ TXDATA[9]/TXCMD[2] 53 RXDATA[ RESET Page [+] Feedback ...

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... HIGH, the information on TXCMD[1:0] is captured as one of four possible COMMANDs, and the information on the TXDATA[9:0] bits are ignored. If TXSC/D is LOW, the information on TXDATA[9:0] is captured as one of 1024 possible 10-bit DATA values, and the information on the TXCMD[1:0] bus is ignored. When the encoder is bypassed (ENCBYP is LOW) TXSC/D is ignored CY7C9689A Page [+] Feedback ...

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... LOW, TXFULL toggles at the character rate to provide a character rate reference control-indication since REFCLK is operating at twice of the data rate. The asserted state of this output (HIGH or LOW) is determined by the state of the EXTFIFO input. When EXTFIFO is LOW, TXFULL is active LOW. When EXTFIFO is HIGH, TXFULL is active HIGH. CY7C9689A Page [+] Feedback ...

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... RXDATA[7:0] outputs. When the Receive FIFO is disabled (FIFOBYP is LOW), these outputs change on the rising edge of the RXCLK output. When the Receive FIFO is enabled (FIFOBYP is HIGH), these outputs change on the rising edge of RXCLK input. RXEN is the three-state control for RXDATA[7:0]. CY7C9689A Page [+] Feedback ...

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... RXCMD[1:0] contains a new COMMAND and the DATA on the RXDATA[9:0] remain unchanged. If RXSC/D is LOW, RXDATA[9:0] contains a new DATA character and the COMMAND output on RXCMD[1:0] remain unchanged. When the decoder is bypassed (ENCBYP is LOW) RXSC/D is not used and may be left unconnected. RXEN is a three-state control for RXSC/D. CY7C9689A Page [+] Feedback ...

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... JK sync character (if BYTE8/10 is HIGH) or the 12-bit LM sync character (if BYTE8/10 is LOW). Framing is disabled when RFEN is LOW. The deassertion of RFEN freezes the character boundary relationship between the serial stream and character clock. RFEN is an asynchronous input, sampled by the internal Receive PLL character clock. CY7C9689A Page [+] Feedback ...

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... RXCMD output pins. When the Receive FIFO is bypassed (FIFOBYP is LOW), RXEMPTY is deasserted whenever data is ready. The asserted state of this output (HIGH or LOW) is determined by the state of the EXTFIFO input. When EXTFIFO is LOW, RXEMPTY is active LOW. When EXTFIFO is HIGH, RXEMPTY is active HIGH. CY7C9689A Page [+] Feedback ...

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... Speed Select. Used to select from one of two operating serial rates for the CY7C9689A. When SPDSEL is HIGH, the signaling rate is between 100 and 200 MBaud. When LOW, the signaling rate is between 50 and 100 MBaud. Used in combination with RANGESEL and BYTE8/10 to configure the VCO multipliers and dividers ...

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... CURSETA or CURSETB should be connected to V Differential Serial Data Inputs. These inputs accept the serial data stream for deserialization and decoding. Only one serial stream at a time may be fed to the receive PLL to extract the data content. This stream is selected using the A/B input. CY7C9689A . DD Page [+] Feedback ...

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... HIGH during normal operation. Power for PECL-compatible I/O signals and internal circuits. Ground for PECL-compatible I/O signals and internal circuits. Power for TTL I/O signals and internal circuits. Ground for TTL I/O signals and internal circuits. CY7C9689A Page [+] Feedback ...

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... The CY7C9689A offers a large feature set, allowing used in a wide range of host systems. Some of the configu- ration options are • ...

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... CY7C9689A TAXI HOTLink Transceiver Block Diagram Description Transmit Input/Output Register The CY7C9689A provides a synchronous interface for data and command inputs, instead of the TAXI’s asynchronous strobed interface. The Transmit Input Register, shown in Figure 2, captures the data and command to be processed by the HOTLink Transmitter, and allows the input timing to be made compatible with asynchronous or synchronous host system buses ...

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... It is enabled by setting EXTFIFO LOW. In shared bus timing, the TXEMPTY and TXFULL outputs and TXEN input are all active LOW signals. If the CY7C9689A is addressed by asserting CE LOW, it becomes “selected” when TXEN is asserted LOW. Following selection, data or command is written into the Transmit FIFO on every clock cycle where TXEN remains LOW ...

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... The CY7C9689A contains an integrated 4B/5B encoder that accepts 8-bit data characters and converts these into 10-bit transmission characters that have been optimized for transport on serial communications links. This 4B/5B encoding scheme is compliant with the ANSI X3T9.5 (FDDI) committee’s 4B/5B code. The CY7C9689A also contains a 5B/6B encoder that accepts 10-bit data characters and converts these into 12-bit transmission characters ...

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... Controller state machine. The clock multiplier PLL can accept a REFCLK input between 8 MHz and 40 MHz, however, this clock range is limited by the operation mode of the CY7C9689A as selected by the SPDSEL and RANGESEL inputs, and to a limited extent, by the BYTE8/10 and FIFOBYP signals. The operating serial ...

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... CY7C9689A If RFEN is LOW, the framer is disabled and no changes are made to character boundaries. The framer in the CY7C9689A operates by shifting the internal character position to align with the character clock. This ensures that the recovered clock does not contain any signif- icant phase changes/hops during normal operation or framing, and allows the recovered clock to be replicated and distributed to other circuits using PLL-based logic elements ...

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... Cascade operation, these same signals are all active HIGH. Either timing model supports connection to various host bus interfaces, state machines, or external FIFOs for depth expansion (see Figure 4) Figure 4. External FIFO Depth Expansion of the CY7C9689A Receive Data Path) CY7C42x5 FIFO EF* EF* FF* ...

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... Machine. Receive Output Register The Receive Output Register changes in response to the rising edge of RXCLK. The Receive FIFO status flag outputs of this register are placed in a High-Z state when the CY7C9689A is not addressed (CE is sampled HIGH). The CY7C9689A D.4B D.23 D.11 D.04 D ...

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... RXD[1] RXDATA[1] RXD[2] RXDATA[2] RXD[3] RXDATA[3] RXD[4] RXDATA[4] RXD[5] RXDATA[5] RXD[6] RXDATA[6] RXD[7] RXDATA[7] RXD[8] RXDATA[8] RXD[9] RXDATA[9] RXCMD[1] RXCMD[0] VLTN CY7C9689A Pre-encoded 12-bit [9] Character Stream [10, 12] RXD[0] RXD[1] RXD[2] RXD[3] RXD[4] RXD[5] RXD[6] RXD[7] RXD[8] [9] RXD[9] [12] RXD[10] RXD[11] Page [+] Feedback ...

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... Storage Temperature ................................. –65°C to +150°C Ambient Temperature with (Power Applied) –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +6.5V DC Voltage Applied to Outputs ..............–0. Output Current into TTL Outputs (LOW) ...................... Input Voltage....................................–0. CY7C9689A DC Electrical Characteristics Parameter Description TTL Outputs V Output HIGH Voltage ...

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... CY7C9689A DC Electrical Characteristics Parameter Description Miscellaneous [15] I Power Supply Current DD Capacitance [16] Parameter Description C TTL Input Capacitance INTTL C PECL input Capacitance INPECL AC Test Loads and Waveforms OUTPUT R1=500Ω C R2=333Ω L ≤ (Includes fixture and probe capacitance) (a) TTL AC Test Load 3.0V 3.0V 2 ...

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... CY7C9689A Transmitter TTL Switching Characteristics, FIFO Enabled Parameter f TXCLK Clock Cycle Frequency With Transmit FIFO Enabled TS t TXCLK Period TXCLK t TXCLK HIGH Time TXCPWH t TXCLK LOW Time TXCPWL [16] [18] t TXCLK Rise Time TXCLKR [16] [18] t TXCLK Fall Time TXCLKF t Flag Access Time From TXCLK↑ to Output ...

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... Sample of CE LOW by REFCLK↑ to Flag Output Valid REFOE t Sample of CE HIGH by REFCLK↑ to Flag Output High-Z REFAZ CY7C9689A Receiver TTL Switching Characteristics, FIFO Bypassed Parameter [20] f RXCLK Clock Output Frequency—100 to 200 MBaud 8-bit Operation ROS (SPDSEL is HIGH and BYTE8/10 is HIGH) RXCLK Clock Output Frequency— ...

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... CY7C9689A REFCLK Input Switching Characteristics Parameter Description f REFCLK Clock Frequency—50 to 100 MBaud, REF 10-bit Mode, REFCLK = 2x Character Rate REFCLK Clock Frequency—50 to 100 MBaud, 8-bit Mode, REFCLK = 2x Character Rate REFCLK Clock Frequency—50 to 100 MBaud, 10-bit Mode, REFCLK = 4x Character Rate REFCLK Clock Frequency— ...

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... PECL Output Fall Time 80−20% (PECL Test Load) FALL t Deterministic Jitter (peak-peak) DJ [16, 30] t Random Jitter (σ Transmitter Total Output Jitter (peak-peak) JT CY7C9689A HOTLink Transmitter Switching Waveforms Write Cycle Asynchronous (FIFO) Interface EXTFIFO = HIGH FIFOBYP = HIGH t TXCPWH TXCLK TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] ...

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... CY7C9689A HOTLink Transmitter Switching Waveforms Write Cycle Asynchronous (FIFO) Interface EXTFIFO = LOW FIFOBYP = HIGH TXCLK TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN TXFULL TXHALF TXEMPTY OUTPUT ENABLE Timing Asynchronous (FIFO) Interface EXTFIFO = HIGH FIFOBYP = HIGH TXCLK TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] ...

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... CY7C9689A HOTLink Transmitter Switching Waveforms OUTPUT ENABLE Timing Asynchronous (FIFO) Interface EXTFIFO = LOW FIFOBYP = HIGH TXCLK TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN CE TXRST t TXCES CE TXRST TXFULL TXHALF TXEMPTY Write Cycle Synchronous Interface t EXTFIFO = HIGH REFH FIFOBYP = LOW REFCLK TXHALT TXSC/D ...

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... CY7C9689A HOTLink Transmitter Switching Waveforms Write Cycle Synchronous Interface EXTFIFO = LOW FIFOBYP = LOW REFCLK TXHALT TXSC/D TXDATA[7:0] XDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN TXFULL TXHALF TXEMPTY OUTPUT ENABLE Timing Synchronous Interface EXTFIFO = HIGH FIFOBYP = LOW REFCLK TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN ...

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... CY7C9689A HOTLink Transmitter Switching Waveforms OUTPUT ENABLE Timing Synchronous Interface EXTFIFO = LOW FIFOBYP = LOW REFCLK TXHALT TXSC/D TXDATA[7:0] TXDATA[9:8]/TXCMD[2:3] TXCMD[1:0] TXEN CE TXFULL TXEMPTY Document #: 38-02020 Rev. *D CY7C9689A (continued) NO OPERATION Page [+] Feedback ...

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... CY7C9689A HOTLink Receiver Switching Waveforms Read Cycle Asynchronous (FIFO) Interface EXTFIFO = HIGH FIFOBYP = HIGH t RXCLKOD t RXCPWH RXCLK t t RXENS RXENH RXEN READ Note 36 RXEMPTY RXFULL RXHALF RXDATA[7:0] RXDATA[9:8/RXCMD[2:3] RXCMD[1:0] CE Read Cycle Asynchronous (FIFO) Interface EXTFIFO = LOW FIFOBYP = HIGH RXCLK t RXENS t RXENH ...

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... CY7C9689A HOTLink Receiver Switching Waveforms Output Enable Timing RXCLK RXEN RXRST t RXCES CE RXFULL RXDATA[7:0] RXDATA[9:8/RXCMD[2:3] RXCMD[1:0] REFCLK Static Alignment t /2− ± INA ± INB SAMPLE WINDOW Table 7. HOTLink TAXI-compatible Encoder Patterns 4B/5B Encoder HEX 4-bit Binary [41] Data Data 0 0000 1 0001 Notes 39 ...

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... Table 8. HOTLink TAXI Compatible Command Symbols CY7C9689A (Transmitter) Command Input TXCMD[3:0] [44] HEX Binary CMD 8-bit mode (BYTE8/10 is HIGH) 0 0000 Note 44. Signals labeled in italics are internal to the CY7C9689A. Document #: 38-02020 Rev. *D 5-bit Encoded HEX 5-bit Binary [42, 43] Symbol Data Data 10100 02 10101 ...

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... CY7C9689A HOTLink Transmit-Path Description. In the receive section of the CY7C9689A, serial data is sampled by the receiver on one of the INx± differential line receiver inputs. The receiver clock and data recovery PLL locks onto the selected serial bit stream and generates an internal bit-rate sample clock. The bit stream is deserialized, decoded, and presented to the Receive FIFO, along with a character clock ...

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... BYTE8/10 is HIGH (as selected by the SPDSEL and RANGESEL inputs) to generate the serial data bit-clock. In this mode, part of the TXCMD bus inputs are used as part of the data input bus. To place the CY7C9689A into synchronous modes, FIFOBYP must be LOW. This mode is usually used for products containing external encoders or scramblers, that must meet specific protocol Document #: 38-02020 Rev ...

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... Asynchronous Decoded In Asynchronous Decoded mode, both the Receive FIFO and the Decoder of the CY7C9689A are enabled. The deserializer operates synchronous to the recovered bit-clock, which is divided generate the Receive FIFO write clock. Characters are read from the Receive FIFO, using the external RXCLK input, when addressed by CE and selected by RXEN ...

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... Enable RX BIST BIST Enable Inputs There are separate BIST enable inputs for the transmit and receive paths of the CY7C9689A. These inputs are both active LOW; i.e., BIST is enabled in its respective section of the device when the BIST enable input is determined logic-0 level. Both BIST enable inputs are asynchronous; i.e., they are synchronized inside the CY7C9689A to the internal state machines ...

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... FIFO status flags remain in a high-Z state and the loop event is lost. This is also true of the VLTN output, such that if the CY7C9689A receive path is not selected to enable the RXDATA bus three-state drivers, the detection of a BIST miscompare is lost. ...

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... Shared Bus. The maximum TXCLK and RXCLK frequency is 50 MHz, which provides a total bandwidth of 50Million characters per second in each direction. More than two CY7C9689A can be serviced on the same bus at full serial line speed. The CY7C9689A is designed to be the Slave in Master-Slave type of shared bus architecture ...

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... Synchronous With Shared Bus Timing and Control (Transmit FIFO Bypassed) When the Transmit FIFO is bypassed (FIFOBYP is LOW and not in byte-packed mode), the CY7C9689A must still be selected to write data into the Transmit Input Register. When CE is sampled LOW and TXRST is sampled HIGH by the rising edge of REFCLK, a Tx_Match condition is generated ...

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... This Rx_Match condition continues until CE is sampled HIGH or RXRST is sampled LOW at the rising edge of RXCLK input. When an Rx_Match (or Rx_RstMatch) condition is present, the RXEMPTY and RXFULL output drivers are enabled. When an Rx_Match (or Rx_RstMatch) condition is not present, these same drivers are disabled (High-Z). CY7C9689A D3 Page [+] Feedback ...

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... Synchronous With UTOPIA Timing and Control (Receive FIFO Bypassed) When the Receive FIFO is bypassed (FIFOBYP is LOW), the CY7C9689A must still be selected to enable the output drivers for the RXDATA bus. With the Receive FIFO bypassed, RXCLK becomes a synchronous output clock operating at the character rate ...

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... The Receive FIFO reset Address Match is shown in Note that while the FIFO flags remain asserted for more than one clock cycle, this is due to an Rx_Match condition, not a continuation of the Rx_RstMatch. CY7C9689A D3 Valid Figure 12. ...

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... This is shown in implementation, a Transmit FIFO reset can never be initiated with TXEN asserted at the same time as TXRST. Since CE is always LOW, any assertion of TXEN causes the Transmit FIFO to be selected, clearing the reset counter. CY7C9689A Figure 15. Figure . In a single-PHY Page ...

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... Tx_FIFO_Reset TXFULL Notes 48. Signals shown as dotted lines indicate timing and levels when configured for external FIFOs (EXTFIFO is HIGH). 49. Signal names listed in italics are internal signals, shown for reference only. Document #: 38-02020 Rev. *D Note 48 Note 48 Not Full CY7C9689A Full Page [+] Feedback ...

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... Document #: 38-02020 Rev. *D Note 48 Note 48 Not Full Figure 15. Transmit FIFO Reset Sequence Note 48 Not Full Note 48 initiate a reset operation. This is shown by the TXFULL flag remaining HIGH (deasserted) following what would be the normal expiration of the seven-state reset counter. CY7C9689A Full Page [+] Feedback ...

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... EMPTY when the internal reset is complete, there is no secondary indication of the completion of the internal reset of the Receive FIFO. The Receive FIFO is usable as soon as new data is placed into it by the Receive Control State Machine Figure 16. Receive FIFO Reset Sequence. Note 48 Not Empty CY7C9689A Empty Page [+] Feedback ...

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... MLC X7R Via to V plane DD Via to V plane SS This is a typical printed circuit board layout showing example placement of power supply bypass components and other components mounted on the same side as the CY7C9689A. Ordering Information Ordering Code Package Name CY7C9689A-AC A100 CY7C9689A-AXC A100 CY7C9689A-AXI A100 Document #: 38-02020 Rev ...

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... MAX. 0.50 A TYP. DETAIL 51 50 12°±1° (8X) TOP LEFT CORNER CHAMFER 1.40±0.05 A SEE DETAIL CY7C9689A R 0.08 MIN. 0° MIN. 0.20 MAX. 0.25 GAUGE PLANE 0°-7° 0.60±0.15 0.20 MIN. 1.00 REF. NOTE: PKG. CAN HAVE OR 4 CORNERS CHAMFER ...

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... Document #: 38-02020 Rev. *D ® Transceiver Description of Change SZV Changed from Spec number: 38-00758 to 38-02020 SPN Changed part number: CY7C9689 to CY7C9689A REV Removed parity reference Deleted mention of Byte-packer Fixed formatting to change mF to µF REV Changed pins 23 and 29 to RXDATA[11:10]/RXCMD[1:0] LFI was changed from “three state” to just output pin ...