HBLXT9781HC.C4 Intel, HBLXT9781HC.C4 Datasheet
HBLXT9781HC.C4
Specifications of HBLXT9781HC.C4
Related parts for HBLXT9781HC.C4
HBLXT9781HC.C4 Summary of contents
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... LXT9761/9781 Fast Ethernet 10/100 Multi-Port Transceiver with RMII The LXT9781 is an eight-port PHY Fast Ethernet Transceiver that supports IEEE 802.3 physical layer applications at both 10 Mbps and 100 Mbps. It provides a Reduced Media Independent Interface (RMII) for switching and other independent port applications. The LXT9761 offers the same features and functionality in a six-port device. This data sheet uses the singular designation “ ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Contents 1.0 Pin Assignments and Signal Descriptions 2.0 Functional Description 2.1 Introduction..........................................................................................................21 2.1.1 OSP™ Architecture ................................................................................21 2.1.2 Comprehensive Functionality .................................................................21 2.2 Interface Descriptions..........................................................................................22 2.2.1 10/100 Network Interface .......................................................................22 2.2.1.1 Twisted-Pair Interface ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII 2.8 10 Mbps Operation.............................................................................................. 37 2.8.1 Preamble Handling................................................................................. 37 2.8.2 Dribble Bits............................................................................................. 38 2.8.3 Link Test................................................................................................. 38 2.8.3.1 Link Failure................................................................................ 38 2.8.4 Jabber .................................................................................................... 38 2.9 Monitoring Operations......................................................................................... 38 2.9.1 Monitoring ...
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... Transmit Timing ...............................................................................58 32 Auto-Negotiation and Fast Link Pulse Timing ...................................................59 33 Fast Link Pulse Timing .......................................................................................59 34 MDIO Write Timing (MDIO Sourced by MAC) ....................................................60 35 MDIO Read Timing (MDIO Sourced by PHY) ....................................................60 36 Power-Up Timing ................................................................................................61 37 RESET And Power-Down Recovery Timing ......................................................61 38 PHY Identifier Bit Mapping .................................................................................67 39 LXT97x1 PQFP Specification ...
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... Register Bit Map.................................................................................................. 63 35 Control Register (Address 0)............................................................................... 65 36 Status Register (Address 1) ................................................................................ 65 37 PHY Identification Register 1 (Address 2)........................................................... 66 38 PHY Identification Register 2 (Address 3)........................................................... 67 39 Auto-Negotiation Advertisement Register (Address 4) ....................................... 67 40 Auto-Negotiation Link Partner Base Page Ability Register (Address 5) .............. 68 41 Auto-Negotiation Expansion (Address 6) ............................................................ 69 42 Auto-Negotiation Next Page Transmit Register (Address 7)............................... 69 43 Auto-Negotiation Link Partner Next Page Receive Register (Address 8) ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Revision History Revision Date Datasheet Description 7 ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Figure 1. LXT9781 Block Diagram QSTAT QCLK Management / ADD<4:0> Mode Select MDIO Logic MDC MDINT Register Set TXENn RMII Parallel/Serial TXDn_0 Converter TXDn_1 Mgmt Counters Register Set RXDn_0 Serial to ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII 1.0 Pin Assignments and Signal Descriptions Figure 2. LXT9781 PQFP Pin Assignments GNDD .......1 RXD7_1 .......2 RXD7_0 .......3 CRS_DV7 .......4 RXER7 .......5 TXEN7 .......6 TXD7_0 .......7 TXD7_1 .......8 RXD6_1 .......9 RXD6_0 ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Figure 3. LXT9781 PBGA Pin Assignments LED/ A LED/ N/C N/C QCLK GNDD CFG1_2 CFG2_2 LED/ LED/ B CRS_DV7 N/C GNDD QSTAT CFG0_1 CFG2_3 RXD7 ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Figure 4. LXT9761 PQFP Pin Assignments GNDD ...... 1 RXD5_1 ...... 2 RXD5_0 ...... 3 CRS_DV5 ...... 4 RXER5 ...... 5 TXEN5 ...... 6 TXD5_0 ...... 7 TXD5_1 ...... 8 RXD4_1 ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Table 1. LXT97x1 RMII Signal Descriptions 9761 Pin# 9781 Pin# PQFP PQFP PBGA 92 92 Y15 ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 1. LXT97x1 RMII Signal Descriptions (Continued) 9761 Pin# 9781 Pin# PQFP PQFP PBGA ...
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... MDC I channel. Maximum frequency is 8 MHz. Management Data Input/Output. Bidirectional serial data MDIO I/O channel for PHY/STA communication. Management Data Interrupt. When bit 18 active MDINT OD Low output on this pin indicates status change. Interrupt is cleared when Register 19 is read. Management Disable. When MDDIS is High, the MDIO is disabled from read and write operations ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 3. LXT97x1 Network Interface Signal Descriptions 9761 9781 Pin# Pin# PQFP PQFP PBGA W19, W20 107, 108 107, 108 V20, V19 111, 110 111, 110 P19, P20 121, 122 121, ...
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... Reset. This active Low input is OR’ed with the control register Reset bit I (0.15). When held Low, all outputs are forced to inactive state. Address <4:0>. Sets base address. Each port adds its port number (starting with 0) to this address to determine its PHY address. Port 0 Address = Base + 0. I Port 1 Address = Base + 1. ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 6. LXT97x1 Power Supply Signal Descriptions PQFP 9781 PBGA 1 Pin# Pin# LXT9761/81: 80, 88, 179 A12, B11, B12, Y9, Y10, Y11 LXT9761 Only: 86 15, 31, 52, 67, 193, ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Table 7. LXT97x1 LED Signal Descriptions 9761 9781 Pin# Pin# PQFP PQFP PBGA D12 177 177 LEDS_0 B13 176 176 LEDS_1 C13 175 175 LEDS_2 A14 174 174 LEDS_3 173 173 ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 7. LXT97x1 LED Signal Descriptions (Continued) 9761 9781 Pin# Pin# PQFP PQFP PBGA 183 189 C8 184 190 A8 185 191 D9 180 186 D10 181 187 A9 182 188 ...
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... This data sheet uses the singular designation “LXT97x1” to refer to both devices. 2.1.1 OSP™ Architecture Intel's LXT97x1 incorporates high-efficiency Optimal Signal Processing™ design techniques, combining the best properties of digital and analog signal processing to produce a truly optimal device. The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by as much over an ideal all-analog equalizer ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII 2.2 Interface Descriptions 2.2.1 10/100 Network Interface The LXT97x1 supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or 100 Mbps Ethernet over fiber media (100BASE-FX). Each network interface port consists of ...
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... Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 impedance is high enough that it has no practical effect on the external termination circuit. On the transmit side, Intel’s patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings (refer to designer to match the output waveform to the magnetic characteristics ...
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... PHY ADDR (BASE+2) Port 2 ex. 6 PHY ADDR (BASE+3) Port 3 ex. 7 PHY ADDR (BASE+4) Port 4 ex. 8 PHY ADDR (BASE+5) Port 5 ex. 9 PHY ADDR (BASE+4) Port 6 ex. 10 PHY ADDR (BASE+5) Port 7 ex Ports 6 and 7 not available on the LXT9761. Figure 7. Management Interface Read Frame Structure ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 MII Interrupts The LXT97x1 provides a single interrupt pin available to all ports. Interrupt logic is shown in Figure 9. The LXT97x1 also provides two dedicated interrupt registers for each port. ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII As a matter of good practice, these supplies should be as clean as possible. Typical filtering and decoupling are shown in 2.3.2 Clock Requirements 2.3.2.1 Reference Clock The LXT97x1 requires a ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Figure 10. Initialization Sequence MDIO Control Mode Pass Control to MDIO Interface (Read/Write) Software Reset? Yes Reset MDIO Registers to values read at H/W Control Interface at last Hardware Reset 2.4.3 ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII 2.4.4 Reset The LXT97x1 provides both hardware and software resets. Configuration control of Auto- Negotiation, speed and duplex mode selection is handled differently for each. During a hardware reset, settings for ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Table 9. Hardware Configuration Settings Desired Configuration AutoNeg Speed Duplex Mode Mode Mode Half 10 Full Disabled Half 100 Full Half 100 Full 3 Enabled Half 10/100 Full 1. These pins ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII • After power-up, power-down, or reset, the power-down recovery time, (see page 61), must be exhausted before proceeding. • Set the auto-negotiation advertisement bits. • Enable auto-negotiation (set MDIO bit 0.12 ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 2.6.1 Reference Clock The LXT97x1 requires a 50 MHz reference clock (REFCLK). The LXT97x1 samples the RMII input signals on the rising edge of REFCLK and drives RMII output signals on ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII 2.6.7 4B/5B Coding Operations The 100BASE-X protocol specifies the use of a 5-bit symbol code on the network media. However, data is normally transmitted across the RMII interface in 2-bit nibblets ...
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... PCS Sublayer The Physical Coding Sublayer (PCS) provides the RMII interface, as well as the 4B/5B encoding/ decoding function. For 100TX and 100FX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TXEN is de-asserted. ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Figure 16. Protocol Sublayers LXT97x1 PCS Sublayer PMA Sublayer PMD Sublayer Table 10. 4B/5B Coding 4B Code Code Type ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Table 10. 4B/5B Coding (Continued) 4B Code Code Type IDLE undefined CONTROL undefined undefined undefined undefined undefined undefined INVALID ...
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... MHz. 2.7.2.3 Twisted-Pair PMD Sublayer The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and descrambling, line coding and decoding (MLT-3 for 100TX, Manchester for 10T), as well as receiving, polarity correction, and baseline wander correction functions. Scrambler/Descrambler (100TX Only) The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using an 11-bit, non-data-dependent polynomial ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 2.7.2.4 Fiber PMD Sublayer The LXT97x1 provides a PECL interface for connection to an external fiber-optic transceiver. (The external transceiver provides the PMD function for fiber media.) The LXT97x1 uses an ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII 2.8.2 Dribble Bits The LXT97x1 device handles dribbles bits in all modes. If between 1-4 dribble bits are received, the nibble will be passed across the RMII, padded with 1s if ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Each serial output reports a specific status condition for all ports. Ports 0 through 7 are assigned bits 0:7 in each stream (bits 3 and 4 are not used on the ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII 2.9.3 Per-Port LED Driver Functions The LXT97x1 incorporates three direct drive LEDs per port. On power up all the LEDs will light for approximately 1 second after reset de-asserts. Each LED ...
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... The LXT97x1 sources this status information separated by the signature with respect to the falling edge of the QCLK input. This allows an ASIC to provide only 1 clock output for multiple PHY devices. The ASIC can also select a frequency MHz to operate this interface. Refer to Table 45 on page 71 Figure 19 ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII 2.9.5 Out-of-Band Signalling The LXT97x1 provides an out-of-band signalling option to transfer status information across the RMII receive interface. Enabled when 25.0=1, this feature uses the RXD(1:0) data bus during the ...
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... Table 13. Device ID Register 31:28 27:12 Version Part ID (hex) 2621 (LXT9761) 0000 2635 (LXT9781) 1. The JEDEC 8-bit identifier. The MSB is for parity and is ignored. Intel’s JEDEC (1111 1110) which becomes 111 1110. Datasheet Table 12. Description Capture Shift Update System Function Description ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII 3.0 Application Information 3.1 Design Recommendations The LXT97x1 is designed to comply with IEEE requirements and to provide outstanding receive Bit Error Rate (BER) and long-line-length performance. To achieve maximum performance ...
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... Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Intel recommends filtering the power supply to the analog VCC pins of the LXT97x1. This has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT97x1, which helps line performance. Second, if the VCC planes are laid out correctly, it keeps digital switching noise away from external connectors, reducing EMI problems ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII 3.1.6 The Twisted-Pair Interface Follow standard guidelines for a twisted-pair interface: • Place the magnetics as close as possible to the LXT97x1. • Keep transmit pair traces as short as possible; ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Figure 21. Power and Ground Supply Connections LXT97x1 GNDS RBIAS GNDA VCCT VCCR VCCD GNDD VCCIO Datasheet 22 .01 F .01 F Analog Supply Plane Digital Supply Plane .01 ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Figure 22. Typical Twisted-Pair Interface TPFOP TPFON TPFIP LXT97x1 TPFIN VCCT GNDA 1. The 100 transmit load termination resistor typically required is integrated in the LXT97xx. 2. Magnetics without a receive ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Figure 23. Typical Fiber Interface 50 TPFONn TPFOPn VCCD +3.3V LXT97x1 SD/TPn 82 GNDD TPFINn TPFIPn 1. Refer to fiber transceiver manufacturer’s recommendations for termination circuitry. Example shown above is suitable ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Figure 24. Typical RMII Interface 8 Port MAC TxData RxData SysCLK 50MHz System Clock from Switch ASIC or external source 50 LXT9781 8 TXDn_0 8 TXDn_1 8 TXENn 8 RXDn_0 8 ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Figure 25. Typical Serial LED Interface LEDLATCH LXT9781 LEDCLK LEDS(0) See Detail for LXT9761 configuration. LEDLATCH LEDCLK LEDS(1) LEDLATCH LEDCLK LEDS(2) LEDLATCH LEDCLK LEDS(3) 1. Note: The outputs are always enabled ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII 4.0 Test Specifications Note: Table 15 through Table 31 specifications of the LXT97x1. These specifications are guaranteed by test, except where noted “by design.” Minimum and maximum values listed in conditions ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Table 17. Digital I/O Characteristics Parameter Sym Input current I I Output Low voltage V OL Output High voltage Applies to all pins except RMII pins. Refer to ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 20. 100BASE-TX Transceiver Characteristics (Continued) Parameter Rise/fall time symmetry Duty cycle distortion Overshoot 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Figure 26. 100BASE-TX Receive Timing REFCLK RXD(1:0) TPFI t 3 CRS_DV Table 23. 100BASE-TX Receive Timing Parameters Parameter RXD<1:0>, CRS_DV, RXER setup to REFCLK rising edge RXD<1:0>, CRS_DV, RXER hold from ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 24. 100BASE-TX Transmit Timing Parameters Parameter TXD<1:0> setup to REFCLK rising edge TXD<1:0> hold from REFCLK rising edge TX_EN sampled to TPFO out (Tx latency) TX_EN setup to REFCLK rising ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Figure 29. 100BASE-FX Transmit Timing REFCLK TXD(1:0) TPFO t 4 TX_EN Table 26. 100BASE-FX Transmit Timing Parameters Parameter TXD<1:0> setup to REFCLK rising edge TXD<1:0> hold from REFCLK rising edge TX_EN ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 27. 10BASE-T Receive Timing Parameters Parameter RXD<1:0>, CRS_DV setup to REFCLK rising edge RXD<1:0>, RX_DV hold from REFCLK rising edge TPFI in to CRS_DV asserted TPFI quiet to CRS_DV de-asserted ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Figure 32. Auto-Negotiation and Fast Link Pulse Timing Clock Pulse TPFOP t1 Figure 33. Fast Link Pulse Timing FLP Burst TPFOP t4 Table 29. Auto-Negotiation and Fast Link Pulse Timing Parameters ...
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... LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Figure 34. MDIO Write Timing (MDIO Sourced by MAC) MDC MDIO Figure 35. MDIO Read Timing (MDIO Sourced by PHY) MDC MDIO Table 30. MDIO Timing Parameters Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Figure 36. Power-Up Timing VCC MDIO,etc Table 31. Power-Up Timing Parameters Parameter Voltage threshold Power Up delay 1. Typical values are at 25° C and are for design aid only; not ...
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... Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto- Negotiation” sections of the IEEE 802.3 specification. • Additional registers (16 through 30) are defined in accordance with the IEEE 802.3 specification for adding unique chip functions ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Datasheet 63 ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII 64 Datasheet ...
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... PHY not able to perform 100BASE- PHY able to perform full-duplex 100BASE-X 1.14 100BASE-X Full Duplex 0 = PHY not able to perform full-duplex 100BASE PHY able to perform half-duplex 100BASE-X 1.13 100BASE-X Half Duplex 0 = PHY not able to perform half-duplex 100BASE Read Only LL = Latching Low LH = Latching High 2 ...
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... LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 36. Status Register (Address 1) (Continued) Bit Name 1 = PHY able to operate at 10 Mbps in full-duplex mode 1.12 10 Mbps Full Duplex 0 = PHY not able to operate at 10 Mbps full-duplex mode 1 = PHY able to operate at 10 Mbps in half-duplex mode 1 ...
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... PHY ID Register #1 (Address The Intel The Level One OUI is 00207B hex. Table 39. Auto-Negotiation Advertisement Register (Address 4) Bit Name 1 = Port has ability to send multiple pages. 4.15 Next Page 0 = Port has no ability to send multiple pages. 4.14 Reserved Ignore Remote fault. 4.13 Remote Fault remote fault. ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 39. Auto-Negotiation Advertisement Register (Address 4) (Continued) Bit Name 1 = 100BASE-T4 capability is available 100BASE-T4 capability is not available. (The LXT97x1 does not support 100BASE-T4 but allows ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Table 40. Auto-Negotiation Link Partner Base Page Ability Register (Address 5) (Continued) Bit Name 10BASE Link Partner is 10BASE-T full duplex capable. 5 Link Partner is not ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 42. Auto-Negotiation Next Page Transmit Register (Address 7) Bit Name Acknowledge Will comply with message. 7.12 (ACK2 Can not comply with message Previous ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Table 44. Port Configuration Register (Address 16, Hex 10) Bit Name This bit is ignored by the LXT97x1. SQE 16 Enable Heart Beat. (10BASE- Disable Heart Beat. ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 45. Quick Status Register (Address 17, Hex 11) Bit Name 1 = Auto-negotiation process completed Auto-negotiation process not completed. Auto-Negotiation 17.7 Complete This bit is only valid when ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Table 47. Interrupt Status Register (Address 19, Hex 13) Bit Name 19.15:8 Reserved Ignore Auto-Negotiation Status 19.7 ANDONE 1= Auto-Negotiation has completed. 0= Auto-Negotiation has not completed. Speed Change Status 19.6 ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 48. LED Configuration Register (Address 20, Hex 14) Bit Name 0000 = Display Speed Status (Continuous, Default). 0001 = Display Transmit Status (Stretched). 0010 = Display Receive Status (Stretched). 0011 ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 Table 48. LED Configuration Register (Address 20, Hex 14) (Continued) Bit Name 00 = Stretch LED events Stretch LED events to 60 ms. 20.3:2 LEDFREQ 10 ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 50. Transmit Control Register #1 (Address 28) Bit Name 28.15:4 Reserved Ignore Nominal Differential Amp Bandwidth Bandwidth 01 = Slower 28.3:2 Control 10 = Fastest 11 = Faster ...
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781 6.0 Package Specifications Figure 39. LXT97x1 PQFP Specification 208-Pin Plastic Quad Flat Package Datasheet • Part Number LXT9761HC (6-port model) • ...
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LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII Figure 40. LXT9781 PBGA Specification 272-Lead Plastic Ball Grid Array • Part Number LXT9781BC (8-port model) • Commercial Temperature Range ( 27.00 ±0.20 24.00 ±0.20 8.00 ±0.10 ...