CYP15G0402DXB-BGI Cypress Semiconductor Corp, CYP15G0402DXB-BGI Datasheet
CYP15G0402DXB-BGI
Specifications of CYP15G0402DXB-BGI
Related parts for CYP15G0402DXB-BGI
CYP15G0402DXB-BGI Summary of contents
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... Figure 1. CYP(V)15G0402DXB HOTLink II™ System Connections Note: 1. CYV15G0402DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYP15G0402DXB refers to devices that are not compliant to SMPTE 259M and SMPTE 292M pathological test requirements. CYP(V)15G0402DXB refers to both devices. Cypress Semiconductor Corporation Document #: 38-02057 Rev. *G Quad HOTLink II™ ...
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... Single burst of 44 ones or 44 zeros. 3. Repetitions of 19 ones followed by 1 zero or 19 zeros fol- lowed by 1 one. x10 x10 Phase Align Framer Buffer Serializer Deserializer Deserializer RX TX CYP15G0402DXB CYV15G0402DXB x10 x10 x10 Phase Align Framer Framer Buffer Serializer Deserializer RX RX ...
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... TXCLKC TXPERD TXDD[0..9] TXOPD TXCLKD TXRST PARCTL Document #: 38-02057 Rev. *G Bit-Rate Clock BIST Enable Latch CYP15G0402DXB CYV15G0402DXB = Internal Signal BISTLE BOE[7..0] RBIST[A..D] Output Enable OELE Latch 8 10 OUTA+ OUTA– TXLBA 10 OUTB+ OUTB– TXLBB 10 OUTC+ OUTC– TXLBC TXLBC 10 OUTD+ OUTD– ...
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... RFENC LPEND Receive Signal Monitor IND+ IND– Clock and Data Recovery TXLBD PLL RBIST[A..D] RFEND FRAMCHAR RXRATE RFMODE Document #: 38-02057 Rev. *G CYP15G0402DXB CYV15G0402DXB = Internal Signal TRSTZ TMS JTAG TCLK Boundary Scan TDI Controller TDO LFIA RXDA[0..9] RXOPA COMDETA RXCLKA+ ÷2 RXCLKA– ...
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... GND COMDET RFEN REFCLK RFEN GND [ RXDD GND TXCLKO TXRST TXOPA RFEN GND [0] – A RXDD GND TXCLKO N/C TXCLK TXPER GND [ CYP15G0402DXB CYV15G0402DXB N/C N/C V INB- OUTB- N/C N/C CC N/C N/C V INB+ OUTB+ N/C N/C CC GND GND V TXRATE RXRATE N/C TDO CC ...
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... GND RFEN REFCLK RFEN COMDET GND [ TXDA GND RFEN TXOP TXRST TXCLKO GND [ – TXDA GND TXPER TXCLKA N/C TXCLKO GND [ CYP15G0402DXB CYV15G0402DXB OUTD- IND- V N/C N/C OUTC- INC- CC OUTD+ IND+ V N/C N/C OUTC+ INC+ CC SDASEL PARCTL V LPENB LPENC TMS TDI ...
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... These clocks must be frequency-coherent to REFCLK, but may be offset in phase. The internal operating phase of each input clock (relative to REFLCK or TXCLKO±) is adjusted when TXRST = LOW and locked when TXRST = HIGH. (ground). The HIGH level is usually implemented by direct connection CYP15G0402DXB CYV15G0402DXB . When CC Page ...
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... RXCLKx+ or falling edge of RXCLKx–. When HIGH, the RXCLKx± recovered clock outputs are complementary clocks operating at half the character rate. Data for the associated receive channels should be latched alternately on the rising edge of RXCLKx+ and RXCLKx–. CYP15G0402DXB CYV15G0402DXB ). TXLOCK Page ...
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... Serial Rate Select. This input specifies the operating bit-rate range of both transmit and receive PLLs. LOW = 195–400 MBaud, MID = 400–800 MBaud, HIGH = 800–1500 MBaud. When SPDSEL is LOW, setting TXRATE = HIGH (Half-rate Reference Clock) is invalid. CYP15G0402DXB CYV15G0402DXB th the serial bit-rate) or ...
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... These inputs are passed to and through the BIST Enable Latch when BISTLE is HIGH, and captured in this latch when BISTLE returns LOW. These inputs are passed to and through the Receive Channel Enable Latch when RXLE is HIGH, and captured in this latch when RXLE returns LOW. CYP15G0402DXB CYV15G0402DXB Page [+] Feedback ...
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... REFCLK↑ TXCKSEL = HIGH, the Input Registers for all four transmit channels are clocked with TXCLKA↑. When TXCKSEL is MID, TXCLKx↑ is used as the input register clock for the associated TXDx[9:0] and TXOPx. CYP15G0402DXB CYV15G0402DXB [4] . When Page ...
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... Mode Logic) to provide a source-matched driver for the transmission lines. These drivers accept data from the Transmit Shifters. These outputs have signal swings equiv- alent to that of standard PECL drivers and are capable of driving AC-coupled optical modules or transmission lines. CYP15G0402DXB CYV15G0402DXB This provides a ...
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... All of these conditions must be valid for the Signal Detect block to indicate a valid signal is present. This status is presented on 400–800 the LFIx (Link Fault Indicator) output associated with each receive channel. 800–1500 CYP15G0402DXB CYV15G0402DXB > 100 mV, or 200 mV DIFF powered optical modules. ...
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... When a disabled receive channel is reenabled, the status of the associated LFIx output and data on the parallel outputs for the associated channel may be indeterminate for ms. Document #: 38-02057 Rev. *G CYP15G0402DXB CYV15G0402DXB rate, the LFIx output will be asserted LOW. While the PLL is attempting to re-lock to the incoming data stream, LFIx may be ...
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... LFSR in the attached Transmitter(s). When synchronized with the received data stream, the associated Receiver compares each received character with each character generated by the LFSR and indicates compare errors and BIST status at the COMDETx and RXDx[1:0] bits of the Output Register CYP15G0402DXB CYV15G0402DXB [8] This provides ...
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... RXLE and OELE control signals HIGH to permanently enable their associated latches. Connection of the associated BOE[7:0] signals to a stable HIGH will then enable the respective transmit and receive channels as soon as the TRSTZ signal is deasserted. CYP15G0402DXB CYV15G0402DXB Page [+] Feedback ...
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... WAIT_FOR_BIST state where it monitors the interface for the first character (D0.0) of the next BIST sequence. Also, if the Elasticity Buffer ever hits an overflow/underflow condition, the status is forced to the BIST_START until the buffer is re-centered (approximately nine character periods). CYP15G0402DXB CYV15G0402DXB [14] MID HIGH [15] ...
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... JTAG modes, only boundary scan is supported. This capability is present only on the LVTTL inputs, LVTTL outputs and REFCLK± input. The high-speed serial signals are not part of the JTAG test chain. Document #: 38-02057 Rev. *G CYP15G0402DXB CYV15G0402DXB JTAG ID The JTAG device ID for the CYP(V)15G0402DXB is ‘1C801069’hex. ...
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... Received COMDETX,RXDx[1:0] = BIST_START (101) YES Compare Next Character COMDETX,RXDx[1:0] = BIST_COMMAND_COMPARE (001) Match Command Data or Command Data End-of-BIST State Yes, COMDETX,RXDx[1:0] = BIST_LAST_GOOD (010) Figure 2. Receive BIST State Machine CYP15G0402DXB CYV15G0402DXB Receive BIST Detected LOW RX PLL Out of Lock COMDETX,RXDx[1:0] = BIST_DATA_COMPARE (000) No Page [+] Feedback ...
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... IN Min. ≤ V ≤ Max. 0. Min. ≤ V ≤ Max. 0. Min. ≤ V ≤ Max. CC Vin = Vcc Vin = Vcc/2 Vin = GND 100Ω differential load V 150Ω differential load V CYP15G0402DXB CYV15G0402DXB V CC 3.3V ± 5% 3.3V ± 5% Min. Max. Unit 2 0.4 V –20 –100 mA –20 ...
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... V ILE ≤ 270 ps ≤ Note 24 (d) CML/LVPECL Input Test Waveform requirement still needs to be satisfied. DIFFS = 3.3V 25°C, parallel outputs unloaded, RX channels enabled, and Serial Line Drivers CC A CYP15G0402DXB CYV15G0402DXB Min. Max. Unit V – 1.1 V – 0 – 1.1 V – 0.7 ...
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... For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time. 28. Parallel data output specifications are only valid if all inputs or outputs are loaded with similar DC and AC loads. Document #: 38-02057 Rev. *G Over the Description Description Description CYP15G0402DXB CYV15G0402DXB Min. Max. Unit 19.5 150 MHz 6 ...
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... 25° MHz and t parameters. This means that at faster character rates the REFCLK duty cycle REFH REFL ) = ( 20) (when RXRATE = HIGH 10) (when RXRATE = LOW data is being received REF CYP15G0402DXB CYV15G0402DXB Min. Max. Unit 1.7 ns 0.8 ns -1500 +1500 ppm Min. Max. Unit 5100 ...
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... The rising edge of TXCLKO output has no direct phase relationship to the REFCLK input. Document #: 38-02057 Rev TXCLK t TXCLKH TXCLKL t TXDS t REFCLK t REFL t TREFDS t t REFCLK t REFH Note 34 t TREFDS t REFCLK t REFH t TXCLKO t TXCLKOD– Note 35 CYP15G0402DXB CYV15G0402DXB t TXDH TREFDH t REFL t TREFDS t TREFDH t REFL Page [+] Feedback ...
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... RXOPx Receive Interface Read Timing RXRATE = HIGH RXCLKx+ – RXCLKx RXDx[9:0], COMDETx], RXOPx Document #: 38-02057 Rev REFCLK t t REFH REFL Note 35 t TXCLKO t TXCLKOD– t RXCLKP t RXCLKL t RXDV– t RXDV+ t RXCLKP t RXCLKH t RXDV– t CYP15G0402DXB CYV15G0402DXB (continued) t RXCLKL RXDV+ Page [+] Feedback ...
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... NO CONNECT E01 VCC POWER E02 VCC POWER E03 VCC POWER E04 VCC POWER E17 VCC POWER E18 VCC POWER CYP15G0402DXB CYV15G0402DXB Ball ID Signal Name Signal Type E19 VCC POWER E20 VCC POWER F01 TXPERC LVTTL OUT F02 TXOPC LVTTL IN PU F03 ...
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... TXDA[3] LVTTL IN V15 TXDA[7] LVTTL IN V16 VCC POWER V17 RXDA[9] LVTTL OUT V18 RXDA[5] LVTTL OUT V19 RXDA[2] LVTTL OUT CYP15G0402DXB CYV15G0402DXB Ball ID Signal Name Signal Type V20 RXDA[1] LVTTL OUT W01 TXDD[5] LVTTL IN W02 TXDD[7] LVTTL IN W03 LFID LVTTL OUT W04 RXCLKD– ...
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... Ordering Information Speed Ordering Code Standard CYP15G0402DXB-BGC Standard CYP15G0402DXB-BGI Standard CYV15G0402DXB-BGC Standard CYV15G0402DXB-BGI Standard CYP15G0402DXB-BGXC Standard CYP15G0402DXB-BGXI Standard CYV15G0402DXB-BGXC Standard CYV15G0402DXB-BGXI Package Diagram 256-lead L2 Ball Grid Array ( 1.57 mm) BL256 HOTLink is a registered trademark, and HOTLink II and MultiFrame are trademarks, of Cypress Semiconductor Corporation. ...
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... Updated differences to pin configuration and pin table Added Power-up Requirements RBI Minor change Document Control corrected Document History Page POT Changed CYP15G0402DXB to CYP(V)15G0402DXB type corresponding to Video-compliant parts Reduced the lower limit of the serial signaling rate from 200 Mbaud to 195 Mbaud and changed the associated specifications accordingly PDS ...