LULXT9785MBC.D0S L7WN Intel, LULXT9785MBC.D0S L7WN Datasheet - Page 131

• Manufacturer Part Number: LULXT9785MBC.D0S L7WN
• Manufacturer: Intel

Specifications of LULXT9785MBC.D0S L7WN

• Lead Free Status / RoHS Status: Compliant

Datasheet
Document Number: 249241
Revision Number: 010
Revision Date: 30-May-2006
Table 43. SMII Signal Summary
The Serial MII operates at 125 MHz using a global reference clock and frame synchronization
signal (REFCLK and SYNC). Each port has an individual two-line data interface (TxDatan and
RxDatan). All signals are synchronous to REFCLK.
Data is exchanged in 10-bit serial words. Each word contains one data byte (two nibbles of 4B
coded data) and two status bits. When the port is operating at 100 Mbps, each word contains a new
data byte. When the port is operating at 10 Mbps, each data byte is repeated 10 times.
TxData
SYNC
RxData
REFCLK
•
1. Refer to
Signal
on page 38
Supports per-packet switching between 10 Mbps and 100 Mbps data rates.
Table 7, “SMII Specific Signal Descriptions – PQFP”
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
PHY
MAC
MAC &
PHY
PHY
for detailed signal descriptions.
To
MAC
MAC
PHY
System
From
Transmit data & control
Synchronization
Receive data & control
Synchronization
Purpose
Table 43
summarizes the SMII signals.
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