L-FW322-06-T100-DB LSI, L-FW322-06-T100-DB Datasheet
L-FW322-06-T100-DB
Specifications of L-FW322-06-T100-DB
Related parts for L-FW322-06-T100-DB
L-FW322-06-T100-DB Summary of contents
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... Compliant with IEEE 1394a-2000, Standard for a High Performance Serial Bus (Supplement effort to better serve its customers and the environment, Agere is switching to lead-free packaging on this product (no intentional addition of lead). — Provides two fully compliant cable ports, each supporting 400 Mbits/s, 200 Mbits/s, and 100 Mbits/s traffic — ...
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... TQFP package FW322 Functional Overview The FW322 is a high-performance, PCI bus-based open host controller designed by Agere Systems Inc. for imple- mentation of IEEE 1394a-2000 compliant systems and devices. Link-layer functions are handled by the FW322, uti- lizing the on-chip 1394a-2000 compliant link core and physical layer core. A high-performance and cost-effective solution for connecting and servicing multiple IEEE 1394 (both 1394-1995 and 1394a-2000) peripheral devices can be realized using this PHY/link OHCI device ...
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... PCI BUS PCI Core The PCI core (shown in Figure 2) serves as the interface to the PCI bus. It contains the state machines that allow the FW322 to respond properly when it is the target of the transaction. Also, during 1394 packet transmission or reception, the PCI core arbitrates for the PCI bus and enables the FW322 to become the bus master for reading the different buffer descriptors and management of the actual data transfers to/from host system memory ...
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... The PCI interface provides an interface between the OHCI blocks and the PCI core. It contains an arbiter to select the appropriate OHCI data engine to gain access to the PCI core. In addition, the PCI interface includes a register select function to decode slave accesses to the OHCI core and select data from appropriate sources ...
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... Fetch a descriptor block from host memory. 2. Fetch data specified by the descriptor block from host memory, and place it into the isochronous transmit FIFO. 3. Data in FIFO is read by the link and sent to the PHY core device interface. Isochronous Receive DMA (IRDMA) The isochronous receive DMA (IRDMA) module moves data from the isochronous receive FIFO to host memory ...
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... Fetch complete buffer descriptor block from host memory. 2. Get data from system memory and store into asynchronous transmit (AT) FIFO. 3. Request transfer of data from FIFO to the link core. 4. Handle retries, if any. 5. Handle errors in steps End the transfer if there are no errors. Asynchronous Receive DMA (ASYNC_RX DMA, ...
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... Isochronous Control Timer: contains the logic for the 1394 cycle timer. DataMUX: pipes 1394 data to and from various modules. Interface Control: contains interrupt and registers for the link core. Interfaces with the slave control block of the PCI core. PHY-Link Interface: interfaces with the 1394 physical layer. ...
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... Based on data received from the OHCI block, the link will form packet headers for the 1394 bus. The link will alert the PHY core regarding the availability of the outbound data the link’s function to generate CRC for the outbound data ...
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... The 49.152 MHz clock signal is also supplied to the associated link layer controller (LLC) for synchroniza- tion of the link with the PHY core and is used for resynchronization of the received data. The PHY/link interface is a direct connection and does not provide isolation ...
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... SelfID packet is set to the value of the PC2 pin. The two most significant bits (21 and 22) in the Pwr field are set to a default of 00. The PC2 pin is tied low or high to create a Pwr field of 000 (PC2 low) or 001 (PC2 high). See Section 4.3.4.1 of the IEEE 1394a-2000 specification for additional details ...
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... PCI_AD[24 PCI_CBEN[3] 23 PCI_IDSEL 24 PCI_AD[23] 25 Note: Active-low signals within this document are indicated following the symbol names. Figure 6. Pin Assignments for the FW322 06 T100 Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller PIN #1 IDENTIFIER AGERE FW322 06 T100 FW322 06 T100 V 75 DDA V ...
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... PCI_AD[17] 35 PCI_AD[16] 36 PCI_CBEN[2] 37 PCI_FRAMEN * Active-low signals within this document are indicated following the symbol names Type I Test. Used by Agere for device manufacturing testing. This pin has an internal pull-up resistor so it can be left floating (or tied high) for normal operation. Do not tie this pin Test ...
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... PCI Signaling Indicator. For PCI applications that use a universal expansion board (see PCI Local Bus Specification, Rev. 2.2, Sec- tion 4.1.1), connect this pin to the VI/O pin. For other cases, con- nect this pin to 3.3 V for PCI buses using 3.3 V signaling for PCI buses using 5 V signaling. FW322 06 T100 ...
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... TPB1– 78 TPB1+ 79 TPA1– 80 TPA1+ * Active-low signals within this document are indicated following the symbol names Type I Power-Class Indicator. On hardware reset (RESETN), this input sets the default value of the least significant bit in the Power Class field (Pwr) in the SelfID packet (see Section 4.3.4.1 of the 1394a- 2000 Specification) ...
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... PLLV DD 92 PLLV SS * Active-low signals within this document are indicated following the symbol names. Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller Type Analog I/O Port 1, Twisted-Pair Bias. TPBIAS1 provides the 1.86 V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. When the FW322’ ...
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... Active-low signals within this document are indicated following the symbol names. Note: For those applications when one or more FW322 ports are not wired to a connector, those unused ports may be left unconnected without normal termination. When a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected state. ...
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... Dimensions are in millimeters. 16.00 ± 0.20 14.00 ± 0.20 PIN #1 IDENTIFIER ZONE 100 DETAIL A DETAIL B 0.50 TYP Agere Systems Inc. 1394A PCI PHY/Link Open Host Controller 76 75 GAGE PLANE SEATING PLANE 14.00 ± 0.20 16.00 ± 0. 1.40 ± 0.05 1.60 MAX SEATING PLANE 0 ...
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... Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere is a registered trademark of Agere Systems Inc. Agere Systems and the Agere logo are trademarks of Agere Systems Inc. ...