HC55183ECM Intersil, HC55183ECM Datasheet - Page 14

• Manufacturer Part Number: HC55183ECM
• Manufacturer: Intersil

Specifications of HC55183ECM

• Number Of Channels: 1
• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Longitudinal Balanced: 45
• Operating Supply Voltage (typ): 5/-28V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Loop Current Limit: 45mA
• Operating Temperature Classification: Commercial
• Pin Count: 28
• Mounting: Surface Mount
• Operating Current: 8.5mA
• Operating Supply Voltage (max): 5.25/-75V
• Operating Supply Voltage (min): 4.75/-24V
• Lead Free Status / RoHS Status: Not Compliant

approximately 2.4V
with the output voltage range of the CODEC. The digital
nature of the CODEC ideally suits it for the function of
programmable ringing generator. See Applications.
Logic Control
Ringing patterns consist of silent intervals. The ringing to
silent pattern is called the ringing cadence. During the silent
portion of ringing, the device can be programmed to any
other operating mode. The most likely candidates are low
power standby or forward active. Depending on system
requirements, the low or high battery may be selected.
Loop supervision is provided with the ring trip detector. The ring
trip detector senses the change in loop current when the phone
is taken off hook. The loop detector full wave rectifies the
ringing current, which is then filtered with external components
R
capacitor C
require a trip response time less than 150ms.
Three very distinct actions occur when the devices detects a
ring trip. First, the DET output is latched low. The latching
mechanism eliminates the need for software filtering of the
detector output. The latch is cleared when the operating
mode is changed externally. Second, the VRS input is
disabled, removing the ring signal from the line. Third, the
device is internally forced to the forward active mode.
Power Dissipation
The power dissipation during ringing is dictated by the load
driving requirements and the ringing waveform. The key to valid
power calculations is the correct definition of average and RMS
currents. The average current defines the high battery supply
current. The RMS current defines the load current.
The cadence provides a time averaging reduction in the
peak power. The total power dissipation consists of ringing
power, P
P
The terms t
interval is t
ratio t
The quiescent power of the device in the ringing mode is
defined in Equation 34.
The total power during the ringing interval is the sum of the
quiescent power and loading power:
P
P
RNG
RT
r Q
r
( )
=
and C
R
P
=
=
r Q
:t
P
( )
S
V
r
r
, and the silent interval power, P
BH
×
is 1:2.
RT
R
RT
+
R
------------- -
t
and the silent interval is t
r
V
×
. The resistor R
and t
+
sets the trip response time. Most applications will
t
BH
r
I
BHQ
t
s
×
+
S
I
P-P
P
AVG
+
s
represent the cadence. The ringing
V
×
BL
. The low signal levels are compatible
------------- -
t
–
r
t
+
----------------------------------------- -
Z
×
s
REN
t
I
s
BLQ
RT
14
V
2
RMS
+
sets the trip threshold and the
+
R
V
LOOP
CC
HC55180, HC55181, HC55183, HC55184
S
×
. The typical cadence
I
CCQ
s
.
(EQ. 33)
(EQ. 34)
(EQ. 35)
For sinusoidal waveforms, the average current, I
defined in Equation 36.
The silent interval power dissipation will be determined by
the quiescent power of the selected operating mode.
Forward Loop Back
Overview
The forward loop back mode (FLB, 101) provides test
capability for the device. An internal signal path is enabled
allowing for both DC and AC verification. The internal 600Ω
terminating resistor has a tolerance of ±20%. The device is
intended to operate from only the low battery during this
mode.
Architecture
When the forward loop back mode is initiated internal
switches connect a 600Ω load across the outputs of the Tip
and Ring amplifiers.
FIGURE 10. FORWARD LOOP BACK INTERNAL TERMINATION
DC Verification
When the internal signal path is provided, DC current will
flow from Tip to Ring. The DC current will force DET low,
indicating the presence of loop current. In addition, the ALM
output will also go low. This does not indicate a thermal
alarm condition. Rather, proper logic operation is verified in
the event of a thermal shutdown. In addition to verifying
device functionality, toggling the logic outputs verifies the
interface to the system controller.
AC Verification
The entire AC loop of the device is active during the forward
loop back mode. Therefore a 4-wire to 4-wire level test
capability is provided. Depending on the transhybrid balance
implementation, test coverage is provided by a one or two
step process.
System architectures which cannot disable the transhybrid
function would require a two step process. The first step
would be to send a test tone to the device while on hook and
not in forward loop back mode. The return signal would be
the test level times the gain R
amplifier. Since the device would not be terminated,
cancellation would not occur. The second step would be to
program the device to FLB and resend the test tone. The
I
AVG
=
 
 
2
-- -
π
----------------------------------------- -
Z
REN
V
RMS
RING
+
TIP
R
×
LOOP
2
600Ω
F
/R
A
of the transhybrid
TIP AMP
RING AMP
AVG
(EQ. 36)
, is