PIC16F1507-E/P Microchip Technology, PIC16F1507-E/P Datasheet - Page 139
![3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 PDIP .300in TUBE](/photos/16/12/161290/pdip20_sml.jpg)
PIC16F1507-E/P
Manufacturer Part Number
PIC16F1507-E/P
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 PDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F1507-EML.pdf
(266 pages)
2.PIC16F1507-EML.pdf
(26 pages)
3.PIC16F1507-EML.pdf
(40 pages)
Specifications of PIC16F1507-E/P
Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Package / Case
PDIP-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
- Current page: 139 of 266
- Download datasheet (3Mb)
PIC16(L)F1507
17.0
The Timer1 module is a 16-bit timer/counter with the
following features:
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 2-bit prescaler
• Optionally synchronized comparator out
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
• Special Event Trigger
• Selectable Gate Source Polarity
• Gate Toggle mode
FIGURE 17-1:
DS41586A-page 139
Asynchronous mode only)
From Timer0
T1G
Overflow
To ADC Auto-Conversion
Note 1: ST Buffer is high speed type when using T1CKI.
TIMER1 MODULE WITH GATE
CONTROL
T1GSS
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
T1GPOL
T1CKI
Set flag bit
TMR1IF on
Overflow
0
TIMER1 BLOCK DIAGRAM
1
TMR1ON
T1GTM
TMR1H
TMR1
(1)
t1g_in
(2)
R
D
CK
TMR1L
Q
Q
Preliminary
TMR1CS<1:0>
LFINTOSC
0
1
T1GGO/DONE
Q
Internal
Internal
F
OSC
Clock
Clock
F
OSC
EN
/4
D
• Gate Single-Pulse mode
• Gate Value Status
• Gate Event Interrupt
Figure 17-1
Single Pulse
Acq. Control
T1CLK
11
10
01
00
T1GSPM
T1CKPS<1:0>
T1SYNC
Prescaler
1, 2, 4, 8
TMR1ON
is a block diagram of the Timer1 module.
0
1
2
0
1
Internal
F
Clock
OSC
T1GVAL
TMR1GE
/2
Q1
2011 Microchip Technology Inc.
Synchronized
Synchronize
Interrupt
Clock Input
D
EN
det
det
Sleep input
Q
(3)
Set
TMR1GIF
T1GCON
Data Bus
RD
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