PIC16F1507-E/P Microchip Technology, PIC16F1507-E/P Datasheet - Page 22
![3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 PDIP .300in TUBE](/photos/16/12/161290/pdip20_sml.jpg)
PIC16F1507-E/P
Manufacturer Part Number
PIC16F1507-E/P
Description
3.5KB Flash, 128B RAM, 18 I/O, CLC, CWG, DDS, 10-bit ADC 20 PDIP .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F1507-EML.pdf
(266 pages)
2.PIC16F1507-EML.pdf
(26 pages)
3.PIC16F1507-EML.pdf
(40 pages)
Specifications of PIC16F1507-E/P
Processor Series
PIC16
Core
PIC16F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
3.5 KB
Data Ram Size
128 B
Interface Type
ICSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Package / Case
PDIP-20
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
-
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
-
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
- Current page: 22 of 266
- Download datasheet (3Mb)
TABLE 3-3:
Legend:
C00h
C0Bh
C0Ch
C0Dh
C0Eh
C0Fh
C10h
C11h
C12h
C13h
C14h
C15h
C16h
C17h
C18h
C19h
C1Ah
C1Bh
C1Ch
C1Dh
C1Eh
C1Fh
C20h
C6Fh
C70h
CFFh
Unimplemented
Core Registers
Common RAM
Read as ‘0’
BANK 24
(Table
70h – 7Fh)
(Accesses
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
= Unimplemented data memory locations, read as ‘0’.
3-2)
PIC16(L)F1507 MEMORY MAP (CONTINUED)
C8Ch
C8Dh
C9Ch
C9Dh
CEFh
C80h
C8Bh
C8Eh
C8Fh
C90h
C91h
C92h
C93h
C94h
C95h
C96h
C97h
C98h
C99h
C9Ah
C9Bh
C9Eh
C9Fh
CA0h
CF0h
CFFh
Unimplemented
Core Registers
Common RAM
BANK 25
Read as ‘0’
(Table
70h – 7Fh)
(Accesses
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)
D0Ch
D0Dh
D1Ch
D1Dh
D00h
D0Bh
D0Eh
D0Fh
D10h
D11h
D12h
D13h
D14h
D15h
D16h
D17h
D18h
D19h
D1Ah
D1Bh
D1Eh
D1Fh
D20h
D6Fh
D70h
D7Fh
Unimplemented
Core Registers
Common RAM
BANK 26
Read as ‘0’
(Table
70h – 7Fh)
(Accesses
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)
D8Bh
D8Ch
D8Dh
D8Eh
D9Ah
D9Bh
D9Ch
D9Dh
D9Eh
DA0h
DEFh
DFFh
D80h
D8Fh
D90h
D91h
D92h
D93h
D94h
D95h
D96h
D97h
D98h
D99h
D9Fh
DF0h
Unimplemented
Core Registers
Common RAM
BANK 27
Read as ‘0’
70h – 7Fh)
(Table
(Accesses
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)
E0Ch
E0Dh
E1Ch
E1Dh
E00h
E0Bh
E0Eh
E0Fh
E10h
E11h
E12h
E13h
E14h
E15h
E16h
E17h
E18h
E19h
E1Ah
E1Bh
E1Eh
E1Fh
E20h
E6Fh
E70h
E7Fh
Unimplemented
Core Registers
Common RAM
Read as ‘0’
BANK 28
70h – 7Fh)
(Table
(Accesses
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)
E8Ch
E8Dh
E9Ch
E9Dh
EEFh
E80h
E8Bh
E8Eh
E8Fh
E90h
E91h
E92h
E93h
E94h
E95h
E96h
E97h
E98h
E99h
E9Ah
E9Bh
E9Eh
E9Fh
EA0h
EF0h
EFFh
Unimplemented
Core Registers
Common RAM
Read as ‘0’
BANK 29
70h – 7Fh)
(Table
(Accesses
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)
F0Ch
F0Dh
F1Ch
F1Dh
F00h
F0Bh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
F18h
F19h
F1Ah
F1Bh
F1Eh
F1Fh
F20h
F6Fh
F70h
F7Fh
See
register mapping
Core Registers
Common RAM
BANK 30
(Table
70h – 7Fh)
(Accesses
Table 3-3
details
3-2)
for
F8Ch
F8Dh
F9Ch
F9Dh
FEFh
F80h
F8Bh
F8Eh
F8Fh
F90h
F91h
F92h
F93h
F94h
F95h
F96h
F97h
F98h
F99h
F9Ah
F9Bh
F9Eh
F9Fh
FA0h
FF0h
FFFh
See
register mapping
Core Registers
Common RAM
BANK 31
(Table
70h – 7Fh)
(Accesses
Table 3-3
details
3-2)
for
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