PIC16F1517-E/P Microchip Technology, PIC16F1517-E/P Datasheet
PIC16F1517-E/P
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PIC16F1517-E/P Summary of contents
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... Flash Microcontrollers 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 with nanoWatt XLP Technology Preliminary Data Sheet DS41452B ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Flash Microcontrollers with nanoWatt XLP Technology Devices Included In This Data Sheet: PIC16F151X and PIC16LF151X Devices: • PIC16F1516 • PIC16LF1516 • PIC16F1517 • PIC16LF1517 • PIC16F1518 • PIC16LF1518 • PIC16F1519 • PIC16LF1519 High-Performance RISC CPU: • C Compiler Optimized Architecture • Only 49 Instructions • ...
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... PIC16(L)F1516/7/8/9 PIC16(L)F151X Family Program Device Memory Flash (words) PIC16F1516 8192 PIC16LF1516 PIC16F1517 8192 PIC16LF1517 PIC16F1518 16384 PIC16LF1518 PIC16F1519 16384 PIC16LF1519 FIGURE 1: 28-PIN SPDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16F1516/1518 AND PIC16LF1516/1518 28-Pin SPDIP, SOIC, SSOP V /MCLR/RE3 PP (2) SS /AN0/RA0 AN1/RA1 AN2/RA2 V +/AN3/RA3 ...
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... REF T0CKI/RA4 (1) V /SS /AN4/RA5 CAP V SS CLKIN/OSC1/RA7 CLKOUT/OSC2/RA6 Note 1: Peripheral pin location selected using APFCON register. Default location. 2: Peripheral pin location selected using APFCON register. Alternate location. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8 RB3/AN9/CCP2 2 20 RB2/AN8 3 19 RB1/AN10 PIC16F1516/1518 4 RB0/AN12/INT ...
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... PIC16(L)F1516/7/8/9 FIGURE 3: 40-PIN PDIP PACKAGE DIAGRAM FOR PIC16F1517/1519 AND PIC16LF1517/1519 40-Pin PDIP V /MCLR/RE3 PP (2) SS /AN0/RA0 AN1/RA1 AN2/RA2 V +/AN3/RA3 REF T0CKI/RA4 (1) V /SS /AN4/RA5 CAP AN5/RE0 AN6/RE1 AN7/RE2 CLKIN/OSC1/RA7 CLKOUT/OSC2/RA6 T1CKI/SOSCO/RC0 (1) CCP2 /SOSCI/RC1 CCP1/AN14/RC2 SCL/SCK/AN15/RC3 AN20/RD0 AN21/RD1 Note 1: Peripheral pin location selected using APFCON register. Default location. ...
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... FIGURE 4: 40-PIN UQFN (5X5) PACKAGE DIAGRAM FOR PIC16F1517/1519 AND PIC16LF1517/1519 40-Pin UQFN DT/RX/AN19/RC7 AN24/RD4 AN25/RD5 AN26/RD6 AN27/RD7 INT/AN12/RB0 AN10/RB1 AN8/RB2 Note 1: Peripheral pin location selected using APFCON register. Default location. 2: Peripheral pin location selected using APFCON register. Alternate location. 2011 Microchip Technology Inc. ...
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... PIC16(L)F1516/7/8/9 FIGURE 5: 44-PIN TQFP PACKAGE DIAGRAM FOR PIC16F1517/1519 AND PIC16LF1517/1519 44-Pin TQFP DT/RX/AN19/RC7 AN24/RD4 AN25/RD5 AN26/RD6 AN27/RD7 INT/AN12/RB0 AN10/RB1 AN8/RB2 (2) CCP2 /AN9/RB3 Note 1: Peripheral pin location selected using APFCON register. Default location. 2: Peripheral pin location selected using APFCON register. Alternate location. ...
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... Peripheral pin location selected using APFCON register. Default location. Note 1: Peripheral pin location selected using APFCON register. Alternate location. 2: PIC16(L)F1517/9 only. 3: 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 (2) — — — SS — — — — — — — ...
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... Development Support............................................................................................................................................................... 313 28.0 Packaging Information.............................................................................................................................................................. 317 Appendix A: Revision History............................................................................................................................................................. 333 Index .................................................................................................................................................................................................. 335 The Microchip Web Site ..................................................................................................................................................................... 341 Customer Change Notification Service .............................................................................................................................................. 341 Customer Support .............................................................................................................................................................................. 341 Reader Response .............................................................................................................................................................................. 342 Product Identification System............................................................................................................................................................. 343 DS41452B-page 10 ) ................................................................................................................................ 265 ™ Preliminary 2011 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 to receive the most current information on all of our products. Preliminary DS41452B-page 11 ...
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... PIC16(L)F1516/7/8/9 NOTES: DS41452B-page 12 Preliminary 2011 Microchip Technology Inc. ...
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... Capture/Compare/PWM Modules CCP1 ● CCP2 ● EUSARTs EUSART ● Master Synchronous Serial Ports MSSP ● Timers Timer0 ● Timer1 ● Timer2 ● 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 shows a Table 1-2 ● ● ● ● ● ● ● ● ● ...
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... Note 1: See Table 1-1 for peripherals available on specific devices. 2: PIC16(L)F1517/9 only. 3: RE<2:0>, PIC16(L)F1517/9 only. 4: DS41452B-page 14 Program Flash Memory RAM CPU (Figure 2-1) Temp. ADC FVR Indicator 10-Bit EUSART Timer1 Timer2 Preliminary PORTA PORTB PORTC PORTD (3) PORTE (4) 2011 Microchip Technology Inc. ...
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... High Voltage XTAL = Crystal Peripheral pin location selected using APFCON register Note 1: Peripheral pin location selected using APFCON register 2: PORTD and RE<2:0> available on PIC16(L)F1517/9 only. 3: 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Input Output Type Type TTL CMOS General purpose I/O. AN — ...
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... A/D Channel 25 input. ST CMOS General purpose I/O. AN — A/D Channel 26 input. = Schmitt Trigger input with CMOS levels I (Register 12-1). Default location. (Register 12-1). Alternate location. Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2011 Microchip Technology Inc. ...
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... TTL = TTL compatible input High Voltage XTAL = Crystal Peripheral pin location selected using APFCON register Note 1: Peripheral pin location selected using APFCON register 2: PORTD and RE<2:0> available on PIC16(L)F1517/9 only. 3: 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Input Output Type Type ST CMOS General purpose I/O. AN — ...
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... PIC16(L)F1516/7/8/9 NOTES: DS41452B-page 18 Preliminary 2011 Microchip Technology Inc. ...
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... Section 3.5 “Indirect Addressing” 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 24.0 “Instruction Set Summary” details. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Saving”, for more details. for more Preliminary DS41452B-page 19 ...
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... Power-up Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W Reg Timer Brown-out Reset Preliminary RAM Addr 12 Indirect Addr 12 FSR0 Reg FSR reg FSR reg STATUS Reg STATUS reg STATUS reg MUX MUX MUX 2011 Microchip Technology Inc. ...
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... PCL and PCLATH • Stack • Indirect Addressing TABLE 3-1: DEVICE SIZES AND ADDRESSES Device Program Memory Space (Words) PIC16F1516 PIC16LF1516 PIC16F1517 PIC16LF1517 PIC16F1518 PIC16LF1518 PIC16F1519 PIC16LF1519 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 3.1 Program Memory Organization ...
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... PIC16(L)F1518/9 PC<14:0> 15 Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh 1000h Page 2 17FFh 1800h Page 3 1FFFh Page 4 2000h Page 7 3FFFh 4000h Rollover to Page 0 Rollover to Page 7 7FFFh 2011 Microchip Technology Inc. ...
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... FSR require one extra instruction cycle to complete. Example 3-2 demonstrates access- ing the program memory via an FSR. The HIGH directive will set bit<7> label points to a location in program memory. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants RETLW DATA0 ...
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... Preliminary Table 3-2. For detailed 3-7. BANKx INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON 2011 Microchip Technology Inc. ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the Note 1: second operand. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register 3-1, contains: as ‘ ...
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... PIC16(L)F1516/7 are as shown in Table 3-4, respectively. Preliminary BANKED MEMORY PARTITIONING Memory Region Core Registers (12 bytes) Special Function Registers (20 bytes maximum) General Purpose RAM (80 bytes maximum) Common RAM (16 bytes) maps for PIC16(L)F1516/7 and Table 3-3 and 2011 Microchip Technology Inc. ...
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TABLE 3-3: PIC16(L)F1516/7 MEMORY MAP BANK 0 BANK 1 000h 080h 100h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 00Bh 08Bh 10Bh 00Ch PORTA 08Ch TRISA 10Ch 00Dh PORTB 08Dh TRISB 10Dh 00Eh PORTC 08Eh TRISC 10Eh ...
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TABLE 3-3: PIC16(L)F1516/7 MEMORY MAP (CONTINUED) BANK 8 BANK 9 400h 480h 500h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 40Bh 48Bh 50Bh 40Ch 48Ch 50Ch Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ 46Fh 4EFh ...
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TABLE 3-3: PIC16(L)F1516/7 MEMORY MAP (CONTINUED) Bank 31 F80h Core Registers (Table 3-2) F8Bh F8Ch Unimplemented Read as ‘0’ FE3h STATUS_SHAD FE4h WREG_SHAD FE5h BSR_SHAD FE6h PCLATH_SHAD FE7h FSR0L_SHAD FE8h FSR0H_SHAD FE9h FSR1L_SHAD FEAh FSR1H_SHAD FEBh — FECh FEDh STKPTR ...
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TABLE 3-4: PIC16(L)F1518/9 MEMORY MAP BANK 0 BANK 1 000h 080h 100h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 00Bh 08Bh 10Bh 00Ch PORTA 08Ch TRISA 10Ch 00Dh PORTB 08Dh TRISB 10Dh 00Eh PORTC 08Eh TRISC 10Eh ...
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TABLE 3-5: PIC16(L)F1518/9 MEMORY MAP (CONTINUED) BANK 8 BANK 9 400h 480h 500h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) 40Bh 48Bh 50Bh 40Ch 48Ch 50Ch Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ 41Fh 49Fh ...
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TABLE 3-6: PIC16(L)F1518/9 MEMORY MAP (CONTINUED) BANK 24 BANK 25 C00h C80h D00h Core Registers Core Registers Core Registers (Table 3-2) (Table 3-2) C0Bh C8Bh D0Bh C0Ch C8Ch D0Ch Unimplemented Unimplemented Unimplemented Read as ‘0’ Read as ‘0’ C6Fh CEFh ...
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... Write Buffer for the upper 7 bits of the Program Counter x8Ah x0Bh or INTCON GIE PEIE x8Bh x = unknown unchanged value depends on condition unimplemented, read as ‘0’ reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 can be Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... SWDTEN --01 0110 --01 0110 — — SCS<1:0> -011 1-00 -011 1-00 LFIOFR HFIOFS 0-q0 --00 q-qq --0q xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GO/DONE ADON -000 0000 -000 0000 ADPREF<1:0> 0000 --00 0000 --00 — — 2011 Microchip Technology Inc. ...
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... Legend: Shaded locations are unimplemented, read as ‘0’. PIC16F151X only. Note 1: PIC16(L)F1517/9 only. 2: Unimplemented, read as ‘1’. 3: 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Bit 5 Bit 4 Bit 3 Bit 2 — — — LATE2 — ...
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... Microchip Technology Inc. ...
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... Legend: Shaded locations are unimplemented, read as ‘0’. PIC16F151X only. Note 1: PIC16(L)F1517/9 only. 2: Unimplemented, read as ‘1’. 3: 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Bit 5 Bit 4 Bit 3 Bit 2 — — — Z — ...
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... If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will 0 be loaded with the address BRW If using BRA, the entire PC will be loaded with the signed value of the operand of the BRA instruction. 0 BRA Preliminary 2011 Microchip Technology Inc. ...
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... RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 3.4.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...
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... Program Counter and pop the stack. 0x09 0x08 0x07 STKPTR = 0x06 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address Preliminary 2011 Microchip Technology Inc. ...
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... The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 0x0F Return Address 0x0E Return Address ...
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... Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: DS41452B-page 42 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF Preliminary 2011 Microchip Technology Inc. ...
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... FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 00000 00001 00010 0x00 0x7F Bank 0 Bank 1 Bank 2 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Indirect Addressing 0 7 FSRxH Bank Select 11111 Bank 31 Preliminary ...
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... FIGURE 3-12: 7 FSRnH 0 1 Location Select 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Bank 2 0x16F 0xF20 Bank 30 0xF6F Preliminary the FSR/INDF interface. All PROGRAM FLASH MEMORY MAP FSRnL 0x8000 0x0000 Program Flash Memory (low 8 bits) 0x7FFF 0xFFFF 2011 Microchip Technology Inc. ...
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... Configuration Word 2 at 8008h. The DEBUG bit in Configuration Word 2 is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 by device Preliminary DS41452B-page 45 ...
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... WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled DS41452B-page 46 R/P-1 R/P-1 R/P-1 IESO CLKOUTEN BOREN<1:0> R/P-1 R/P-1 R/P-1 WDTE<1:0> Unimplemented bit, read as ‘1’ Value when blank or after Bulk Erase Preliminary R/P-1 U-1 — bit 8 R/P-1 R/P-1 FOSC<2:0> bit 0 2011 Microchip Technology Inc. ...
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... EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Preliminary DS41452B-page 47 ...
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... R/P-1 DEBUG LPBOR BORV R/P-1 U-1 U-1 (1) VCAPEN — — Unimplemented bit, read as ‘1’ Value when blank or after Bulk Erase (1) pin functions are disabled. CAP Preliminary R/P-1 U-1 STVREN — bit 8 R/P-1 R/P-1 WRT<1:0> bit 0 2011 Microchip Technology Inc. ...
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... See Section 11.4 “User ID, Device ID and Configuration for more information on accessing these Word Access” memory locations. For more information on checksum calculation, see the “PIC16(L)F151X/152X Memory Programming Specification” (DS41442). 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 “Write such as Preliminary DS41452B-page 49 ...
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... Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13-5 DEV<8:0>: Device ID bits Device PIC16F1519 01 0110 111 PIC16F1518 01 0110 110 PIC16F1517 01 0110 101 PIC16F1516 01 0110 100 PIC16LF1519 01 0111 111 PIC16LF1518 01 0111 110 PIC16LF1517 01 0111 101 PIC16LF1516 01 0111 100 bit 4-0 REV< ...
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... Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources • Fast start-up oscillator allows internal circuits to power up and stabilize before switching to the 16 MHz HFINTOSC 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 The oscillator module can be configured in one of eight clock modes. 1. ECL – External Clock Low Power mode (0 MHz to 0 ...
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... HF-500 kHz /32 0111 HF-250 kHz 1001/ /64 0110 HF-125 kHz 1000/ /128 0101 HF-62.5 kHz /256 0100 HF-31.25 kHz 0011 /512 0010 LF-31 kHz 0001 0000 Preliminary Low Power Mode Event Switch (SCS<1:0>) 2 Primary Clock 00 01 INTOSC 1x 2011 Microchip Technology Inc. ...
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... Configuration Word 1: • High power, 4-20 MHz (FOSC = 111) • Medium power, 0.5-4 MHz (FOSC = 110) • Low power, 0-0.5 MHz (FOSC = 101) 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...
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... Start-up mode can be selected (see “Two-Speed Clock Start-up Preliminary CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic R (3) ( Sleep F OSC2/CLKOUT R S (1) ) may be required for S varies with the Oscillator mode F P Oscillator Start-up Timer (OST) Section 5.4 Mode”). 2011 Microchip Technology Inc. ) ...
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... MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288) 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 5.2.1.5 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required ...
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... Watchdog Timer (WDT) Internal • Fail-Safe Clock Monitor (FSCM) The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized. Preliminary Figure 5-1). Select 31 kHz, via for more information. The 2011 Microchip Technology Inc. ...
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... Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transi- tion times can be obtained between frequency changes that use the same oscillator source. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 5.2.2.4 Internal Oscillator Clock Switch Timing ...
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... System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time HFINTOSC IRCF <3:0> System Clock DS41452B-page 58 Start-up Time 2-cycle Sync 0 2-cycle Sync LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync 0 Preliminary Running Running Running 2011 Microchip Technology Inc. ...
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... Word 1, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP modes. The OST does not reflect the status of the secondary oscillator. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 5.3.3 SECONDARY OSCILLATOR The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral ...
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... Oscillator Delay 31 kHz Oscillator Warm-up Delay (T 31.25 kHz-16 MHz DC – 20 MHz 2 cycles DC – 20 MHz 1 cycle of each 32 kHz-20 MHz 1024 Clock Cycles (OST) 2 s (approx.) 31.25 kHz-16 MHz 31 kHz 1 cycle of each 1024 Clock Cycles (OST) Preliminary 2011 Microchip Technology Inc. ) WARM ...
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... OSC1 1022 1023 0 1 OSC2 Program Counter System Clock 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 5.4.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC< ...
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... Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed. Preliminary 2011 Microchip Technology Inc. ...
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... Clock Output Clock Monitor Output (Q) OSCFIF The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in Note: this example have been chosen for clarity. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Oscillator Failure Test Test Preliminary Failure ...
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... Secondary oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Duplicate frequency derived from HFINTOSC. Note 1: DS41452B-page 64 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary U-0 R/W-0/0 R/W-0/0 SCS<1:0> — bit 0 2011 Microchip Technology Inc. ...
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... CONFIG1 7:0 CP MCLRE — = unimplemented location, read as ‘ 0 ’. Shaded cells are not used by clock sources. Legend: 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 R-0/q U-0 HFIOFR — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... PIC16(L)F1516/7/8/9 NOTES: DS41452B-page 66 Preliminary 2011 Microchip Technology Inc. ...
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... External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset LPBOR Reset BOR Enable 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 6-1. PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41452B-page 67 ...
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... Preliminary DD for more information. falls below V for a DD BOR , the device BORDC for more information. Device Operation upon wake- up from Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD 2011 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive BOREN<1:0> bits are located in Configuration Word 1. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 (1) T PWRT < T PWRT PWRT (1) ...
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... Preliminary Section 10.0 for more information. Table 6-4 Section 3.4.2 “Overflow/Underflow Timer configuration. See for more information. Figure 6-3). This 2011 Microchip Technology Inc. ...
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... FIGURE 6-3: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 T PWRT T MCLR T OST Preliminary DS41452B-page 71 ...
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... ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition PCON Register 00-1 110x uu-u 0uuu uu-u 0uuu uu-0 uuuu uu-u uuuu 00-1 11u0 uu-u uuuu uu-u u0uu 1u-u uuuu u1-u uuuu 2011 Microchip Technology Inc. ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 6-2. R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q RWDT ...
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... Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets. DS41452B-page 74 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — RMCLR RI RWDT — WDTPS<4:0> Preliminary Register Bit 1 Bit 0 on Page — BORRDY 69 POR BOR SWDTEN 95 2011 Microchip Technology Inc. ...
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... Many peripherals produce Interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure 7-1. FIGURE 7-1: INTERRUPT LOGIC Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IE) PIE1<0> PIRn<7> PIEn<7> 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 TMR0IF TMR0IE INTF INTE IOCIF IOCIE PEIE GIE Preliminary Wake-up ...
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... The latency for synchronous interrupts instruction cycles. For asynchronous interrupts, the latency instruction cycles, depending on when the interrupt occurs. See and Figure 7-3 for more details. Preliminary 2011 Microchip Technology Inc. Figure 7-2 ...
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... PC Execute 2 Cycle Instruction at PC Interrupt GIE PC PC-1 PC Execute 3 Cycle Instruction at PC Interrupt GIE PC Execute 3 Cycle Instruction at PC 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Interrupt Sampled during Q1 PC+1 0004h Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP FSR ADDR ...
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... INTF is enabled to be set any time during the Q4-Q1 cycles. DS41452B-page (1) (2) Interrupt Latency Inst ( — Dummy Cycle Dummy Cycle Inst (PC) . Synchronous latency = 3 Section 25.0 “Electrical Preliminary 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) , where T = instruction cycle time Specifications”. 2011 Microchip Technology Inc. ...
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... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Preliminary DS41452B-page 79 ...
Page 80
... User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. R/W-0/0 R/W-0/0 R/W-0/0 INTE IOCIE TMR0IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-0/0 R-0/0 INTF IOCIF bit 0 2011 Microchip Technology Inc. ...
Page 81
... Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. ...
Page 82
... Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. U-0 R/W-0/0 U-0 — BCLIE — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2011 Microchip Technology Inc. U-0 R/W-0/0 — CCP2IE bit 0 ...
Page 83
... Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
Page 84
... U-0 R/W-0/0 U-0 — BCLIF — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2011 Microchip Technology Inc. should ensure the U-0 R/W-0/0 — CCP2IF bit 0 ...
Page 85
... TMR1GIE ADIE OSFIE — PIE2 TMR1GIF ADIF PIR1 OSFIF — PIR2 — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts. Legend: 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF TMR0CS TMR0SE PSA ...
Page 86
... PIC16(L)F1516/7/8/9 NOTES: DS41452B-page 86 Preliminary 2011 Microchip Technology Inc. ...
Page 87
... The FVR module is an example of internal circuitry that might be sourcing current. See Section 14.0 “Fixed for more information on this Voltage Reference (FVR)” module. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 8.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1 ...
Page 88
... SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP OST (3) T Interrupt Latency (4) Processor in Sleep Inst( Dummy Cycle Inst( Preliminary 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) 2011 Microchip Technology Inc. ...
Page 89
... Reserved: Read as ‘1’. Maintain this bit set. PIC16F151X only. Note 1: See 2: Section 25.0 “Electrical 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 8.2.2 PERIPHERAL USAGE IN SLEEP Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected ...
Page 90
... BCLIF — — — — — — WDTPS<4:0> Preliminary Register Bit 1 Bit 0 on Page INTF IOCIF 80 IOCBF1 IOCBF0 135 IOCBN1 IOCBN0 135 IOCBP1 IOCBP0 135 TMR2IE TMR1IE 81 — CCP2IE 82 TMR2IF TMR1IF 83 — CCP2IF VREGPM 89 Reserved SWDTEN 95 2011 Microchip Technology Inc. ...
Page 91
... Shaded cells are not used by LDO. Legend: PIC16F151X only. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 On power-up, the external capacitor will load the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor ...
Page 92
... PIC16(L)F1516/7/8/9 NOTES: DS41452B-page 92 Preliminary 2011 Microchip Technology Inc. ...
Page 93
... Configurable time-out period is from 256 seconds (nominal) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41452B-page 93 ...
Page 94
... See Section 3.0 “Memory Organization” Mode The STATUS register information. Active Active Disabled Active Disabled Disabled Preliminary Section 5.0 “Oscillator for more and (Register 3-1) for more WDT Cleared Cleared until the end of OST Unaffected 2011 Microchip Technology Inc. ...
Page 95
... If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ...
Page 96
... IRCF<3:0> — — WDTPS<4:0> Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 FCMEN IESO CLKOUTEN PWRTE WDTE<1:0> Preliminary Register Bit 1 Bit 0 on Page SCS<1:0> SWDTEN 95 Watchdog Timer . Register Bit 9/1 Bit 8/0 on Page BOREN<1:0> — 46 FOSC<2:0> 2011 Microchip Technology Inc. ...
Page 97
... The PMADRH:PMADRL register pair can address maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADRL register. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 11.1.1 PMCON1 AND PMCON2 REGISTERS PMCON1 is the control register for Flash program memory accesses ...
Page 98
... Instruction Fetched ignored the next Preliminary FLASH PROGRAM MEMORY READ FLOWCHART Start READ Operation Select (CFGS) Select Word Address (PMADRH:PMADRL) Initiate READ operation ( NOP execution forced NOP execution forced Data read now in PMDATH:PMDATL End READ Operation 2011 Microchip Technology Inc. ...
Page 99
... Ignored MOVF PMDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 PMADRH,PMADRL PC+3 INSTR ( PMDATH,PMDATL INSTR ( INSTR( INSTR( instruction ignored instruction ignored Forced NOP Forced NOP ...
Page 100
... FIGURE 11-3: FLASH PROGRAM MEMORY UNLOCK SEQUENCE FLOWCHART Start Unlock Sequence Write 055h to PMCON2 Write 0AAh to PMCON2 Initiate WRITE or ERASE operation ( Instruction Fetched ignored NOP execution forced Instruction Fetched ignored NOP execution forced Unlock Sequence Preliminary 2011 Microchip Technology Inc. End ...
Page 101
... This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 FIGURE 11-4: FLASH PROGRAM ...
Page 102
... Write AAh ; Set WR bit to begin erase ; NOP instructions are forced as processor starts ; row erase of program memory The processor stalls until the erase process is complete ; after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary 2011 Microchip Technology Inc. ...
Page 103
... Write opera- tions do not cross these boundaries. At the completion of a program memory write operation, the data in the write latches is reset to contain 0x3FFF. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 The following steps should be completed to load the write latches and program a row of program memory. ...
Page 104
FIGURE 11-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES PMADRH - Row PMADRH<6:0> Address :PMADRL<7:5> Decode ...
Page 105
... Select Program or Config. Memory (CFGS) Select Row Address (PMADRH:PMADRL) Select WRITE Operation (FREE = 0) Load Write Latches Only (LWLO = 1) 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Enable Write/Erase Operation (WREN = 1) Load the value to write (PMDATH:PMDATL) Update the word counter (word_cnt--) Yes Last word to ...
Page 106
... NOP instructions are forced as processor writes ; all the program memory write latches simultaneously ; to program memory. ; After NOPs, the processor ; stalls until the self-write process in complete ; after write processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary 2011 Microchip Technology Inc. ...
Page 107
... Load the starting address of the row to be rewritten. 5. Erase the program memory row. 6. Load the write latches with data from the RAM image. 7. Initiate a programming operation. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 FIGURE 11-7: FLASH PROGRAM MEMORY MODIFY FLOWCHART Start MODIFY Operation READ Operation (Figure x ...
Page 108
... MOVWF PROG_DATA_LO ; Store in user location MOVF PMDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location DS41452B-page 108 11-2, the Function Read Access User IDs Yes Yes Yes Figure 11-2) Figure 11-2) Preliminary Write Access Yes No No 2011 Microchip Technology Inc. ...
Page 109
... RAM. This image will be used to verify the data currently stored in Flash Program Memory. READ Operation (Figure x.x) Figure 11-2 PMDAT = No RAM image ? Yes Fail VERIFY Operation No Last Word ? Yes End VERIFY Operation 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Preliminary DS41452B-page 109 ...
Page 110
... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 PMADR<14:8> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u bit 0 R/W-0/0 R/W-0/0 bit 0 R/W-0/0 R/W-0/0 bit 0 2011 Microchip Technology Inc. ...
Page 111
... Does not initiate a program Flash read. Unimplemented bit, read as ‘1’. Note 1: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started ( The LWLO bit is ignored during a program memory erase operation (FREE = 1). 3: 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 (2) R/W/HC-0/0 R/W/HC-x/q R/W-0/0 FREE ...
Page 112
... VCAPEN — Preliminary W-0/0 W-0/0 W-0/0 bit 0 Register on Bit 1 Bit 0 Page WR RD 111 112 110 110 110 110 INTF IOCIF 80 Register Bit 10/2 Bit 9/1 Bit 8/0 on Page BOREN<1:0> — 46 FOSC<2:0> BORV STVREN — 48 — WRT<1:0> 2011 Microchip Technology Inc. ...
Page 113
... The port has analog functions and has an ANSELx register which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 12-1. 2010 Microchip Technology Inc. PIC16(L)F1516/7/8/9 FIGURE 12-1: D Write LATx Write PORTx ...
Page 114
... CCP2SEL: Pin Selection bit 0 = CCP2 function is on RC1 1 = CCP2 function is on RB3 DS41452B-page 114 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2010 Microchip Technology Inc. R/W-0/0 R/W-0/0 SSSEL CCP2SEL bit 0 ...
Page 115
... The ANSELA register must be initialized Note: to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. 2010 Microchip Technology Inc. PIC16(L)F1516/7/8/9 12.2.2 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The ...
Page 116
... Value at POR and BOR/Value at all other Resets (1) R/W-1/1 R/W-1/1 R/W-1/1 TRISA4 TRISA3 TRISA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/x R/W-x/x RA1 RA0 bit 0 R/W-1/1 R/W-1/1 TRISA1 TRISA0 bit 0 2010 Microchip Technology Inc. ...
Page 117
... Digital I/O. Pin is assigned to port or digital special function Analog input. Pin is assigned as analog input When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin. 2010 Microchip Technology Inc. PIC16(L)F1516/7/8/9 R/W-x/u R/W-x/u R/W-x/u ...
Page 118
... IESO CLKOUTEN PWRTE WDTE<1:0> Preliminary Register Bit 1 Bit 0 on Page ANSA1 ANSA0 117 SSSEL CCP2SEL 114 LATA1 LATA0 117 PS<2:0> 157 RA1 RA0 116 TRISA1 TRISA0 116 Register Bit 9/1 Bit 8/0 on Page BOREN<1:0.> — 46 FOSC<2:0> 2010 Microchip Technology Inc. ...
Page 119
... The ANSELB register must be initialized Note: to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. 2010 Microchip Technology Inc. PIC16(L)F1516/7/8/9 12.3.2 PORTB FUNCTIONS AND OUTPUT PRIORITIES Each PORTB pin is multiplexed with other functions. The ...
Page 120
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATB4 LATB3 LATB2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RB1 RB0 bit 0 R/W-1/1 R/W-1/1 TRISB1 TRISB0 bit 0 R/W-x/u R/W-x/u LATB1 LATB0 bit 0 2010 Microchip Technology Inc. ...
Page 121
... RB6 TRISB TRISB7 TRISB6 WPUB WPUB7 WPUB6 x = unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. Legend: 2010 Microchip Technology Inc. PIC16(L)F1516/7/8/9 R/W-1/1 R/W-1/1 R/W-1/1 ANSB4 ANSB3 ANSB2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) ...
Page 122
... RC3 and RC4 read the Preliminary Table 12-7. Table 12-7. PORTC OUTPUT PRIORITY (1) Function Priority SOSCO RC0 SOSCI CCP2 RC1 CCP1 RC2 SCL SCK (2) RC3 SDA (2) RC4 SDO RC5 CK TX RC6 DT RC7 input when C mode is enabled. 2010 Microchip Technology Inc. ...
Page 123
... Bit is cleared bit 7-0 LATC<7:0>: PORTC Output Latch Value bits Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is the Note 1: return of actual I/O pin values. 2010 Microchip Technology Inc. PIC16(L)F1516/7/8/9 R/W-x/u R/W-x/u R/W-x/u RC4 ...
Page 124
... LATC3 LATC2 RC5 RC4 RC3 RC2 TRISC5 TRISC4 TRISC3 TRISC2 Preliminary U-0 U-0 — — bit 0 Register Bit 1 Bit 0 on Page — — 121 SSSEL CCP2SEL 114 LATC1 LATC0 120 RC1 RC0 120 TRISC1 TRISC0 120 2010 Microchip Technology Inc. ...
Page 125
... PORTD Registers (PIC16F1517/1519 only) PORTD is a 8-bit wide, bidirectional port. The corresponding data direction register (Register 12-16). Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i ...
Page 126
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATD4 LATD3 LATD2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RD1 RD0 bit 0 R/W-1/1 R/W-1/1 TRISD5 TRISD4 bit 0 R/W-x/u R/W-x/u LATD1 LATD0 bit 0 2010 Microchip Technology Inc. ...
Page 127
... LATD LATD7 LATD6 PORTD RD7 RD6 TRISD TRISD7 TRISD6 x = unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTD. Legend: PIC16F1517/1519 only. Note 1: 2010 Microchip Technology Inc. PIC16(L)F1516/7/8/9 R/W-1/1 R/W-1/1 R/W-1/1 ANSD4 ANSD3 ANSD2 U = Unimplemented bit, read as ‘0’ ...
Page 128
... Pins configured as analog inputs will read ‘0’. DS41452B-page 128 12.6.2 PORTE FUNCTIONS AND OUTPUT PRIORITIES PORTE has no peripheral outputs, so the PORTE output has no priority function. 12-19) reads are pins are Preliminary 2010 Microchip Technology Inc. ...
Page 129
... TRISE<2:0>: RE<2:0> Tri-State Control bits 1 = PORTE pin configured as an input (tri-stated PORTE pin configured as an output TRISE<2:0> are not implemented on the PIC16(L)F1517/9. Read as ‘0’. Note 1: Unimplemented, read as ‘1’. 2: 2010 Microchip Technology Inc. PIC16(L)F1516/7/8/9 U-0 R-x/u R/W-x/u (1) RE3 RE2 — ...
Page 130
... Value at POR and BOR/Value at all other Resets (1) (2) U-0 U-0 R/W-1 ANSE2 — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) . Digital input buffer disabled. Preliminary 2010 Microchip Technology Inc. R/W-x/u R/W-x/u LATE1 LATE0 bit 0 R/W-1 R/W-1 ANSE1 ANSE0 bit 0 ...
Page 131
... Bit -/6 13:8 CONFIG1 7:0 CP MCLRE — = unimplemented location, read as ‘ 0 ’. Shaded cells are not used by PORTE. Legend: 2010 Microchip Technology Inc. PIC16(L)F1516/7/8/9 U-0 R/W-1/1 WPUE3 — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 132
... PIC16(L)F1516/7/8/9 NOTES: DS41452B-page 132 Preliminary 2010 Microchip Technology Inc. ...
Page 133
... A pin can be configured to detect rising and falling edges simultaneously by setting both the IOCBPx bit and the IOCBNx bit of the IOCBP and IOCBN registers, respectively. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 13.3 Interrupt Flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of PORTB ...
Page 134
... INTERRUPT-ON-CHANGE BLOCK DIAGRAM IOCBNx RBx IOCBPx Q4Q1 Q4Q1 DS41452B-page 134 Q4Q1 edge detect data bus = write IOCBFx CK from all other IOCBFx individual pin detectors Q4Q1 Preliminary to data bus IOCBFx IOCIE IOC interrupt to CPU core Q3 Q4 Q4Q1 2011 Microchip Technology Inc. ...
Page 135
... An enabled change was detected on the associated pin. Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge was detected on RBx change was detected, or the user cleared the detected change. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 R/W-0/0 R/W-0/0 ...
Page 136
... IOCBP2 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBF5 IOCBF4 IOCBF3 IOCBF2 TRISB5 TRISB4 TRISB3 TRISB2 Preliminary Register Bit 1 Bit 0 on Page ANSB1 ANSB0 117 INTF IOCIF 80 IOCBP1 IOCBP0 135 IOCBN1 IOCBN0 135 IOCBF1 IOCBF0 135 TRISB1 TRISB0 116 2011 Microchip Technology Inc. ...
Page 137
... BOR BOREN<1:0> and BORFS = 1 BOREN<1:0> and BORFS = 1 LDO All PIC16F151X devices, when VREGPM = 1 and not in Sleep 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC module is routed through a programmable gain amplifier. The amplifier can be configured to amplify the reference , with 1 ...
Page 138
... Value at POR and BOR/Value at all other Resets q = Value depends on condition (1) (Low Range) (High Range Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG — — Preliminary U-0 R/W-0/0 R/W-0/0 — ADFVR<1:0> bit 0 (2) (2) Register Bit 1 Bit 0 on page ADFVR<1:0> 138 2011 Microchip Technology Inc. ...
Page 139
... The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 FIGURE 15-1: 15.2 Minimum Operating V ...
Page 140
... PIC16(L)F1516/7/8/9 NOTES: DS41452B-page 140 Preliminary 2011 Microchip Technology Inc. ...
Page 141
... Temp Indicator FVR Buffer1 CHS<4:0> Note 1: When ADON = 0, all multiplexer inputs are disconnected. 2: See ADCON0 register 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) ...
Page 142
... Unless using the F Note: system clock frequency will change the ADC adversely affect the ADC result. Section 16.2 Preliminary peri- AD Figure 16-2. specifica- AD for Table 16-1 gives examples of appro- , any changes in the RC clock frequency, which may 2011 Microchip Technology Inc. ...
Page 143
... Sleep mode. FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2011 Microchip Technology Inc. PIC16(L)F1516/7/8 DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 16 MHz 8 MHz (2) (2) 125 ns 250 ns (2) (2) 250 ns 500 ns (2) 0.5 s (2) 1.0 ...
Page 144
... ADCON1 register controls the output format. Figure 16-3 shows the two output formats. ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result Preliminary ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 2011 Microchip Technology Inc. ...
Page 145
... A device Reset forces all registers to their Note: Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 16.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...
Page 146
... MOVF ADRESL,W MOVWF RESULTLO Preliminary A/D CONVERSION ; ;clock ;Vdd and Vss Vref ; ;Set RA0 to input ; ;Set RA0 to analog ; ;Turn ADC On ;Acquisiton delay ;No, test again ; ;Read upper 2 bits ;store in GPR space ; ;Read lower 8 bits ;Store in GPR space 2011 Microchip Technology Inc. ...
Page 147
... Note 1: Section 14.0 “Fixed Voltage Reference (FVR)” See 2: Section 15.0 “Temperature Indicator Module” AN<7:5> and AN<27:20> are PIC16(L)F1517/9 only. 3: 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (2) ...
Page 148
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets DD (1) + pin REF + pin as the source of the positive reference, be aware that a REF Section 25.0 “Electrical Specifications” Preliminary R/W-0/0 R/W-0/0 ADPREF<1:0> bit 0 (1) for details. 2011 Microchip Technology Inc. ...
Page 149
... Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0> : ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved : Do not use. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 150
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u ADRES<9:8> bit 0 R/W-x/u R/W-x/u bit 0 2011 Microchip Technology Inc. ...
Page 151
... REF 2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources . This is required to meet the pin leakage specification. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...
Page 152
... V - REF DS41452B-page 152 V DD Sampling Switch 0. Rss R IC LEAKAGE (1) I 0. Full-Scale Range 0.5 LSB Zero-Scale Full-Scale Transition V REF Transition Preliminary HOLD REF Sampling Switch (k ) Analog Input Voltage 1.5 LSB + 2011 Microchip Technology Inc. ...
Page 153
... TRISC6 (1) TRISD TRISD7 TRISD6 TRISE — — — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. Legend: PIC16(L)F1517/9 only. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> — — ANSA2 ANSA5 — ANSA3 ...
Page 154
... PIC16(L)F1516/7/8/9 NOTES: DS41452B-page 154 Preliminary 2011 Microchip Technology Inc. ...
Page 155
... OSC 0 T0CKI 1 TMR0SE TMR0CS 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 17.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on either the rising or falling edge of the T0CKI pin. The edge that increments the counter is determined by the TMR0SE bit in the OPTION_REG register. TMR0SE = 1 selects the falling edge ...
Page 156
... Section 25.0 “Electrical . Specifications” 17.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41452B-page 156 Preliminary 2011 Microchip Technology Inc. ...
Page 157
... Timer0 Module Register TRISA TRISA7 TRISA6 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ ...
Page 158
... PIC16(L)F1516/7/8/9 NOTES: DS41452B-page 158 Preliminary 2011 Microchip Technology Inc. ...
Page 159
... T1OSCEN (1) Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 • Gate Toggle mode • Gate Single-pulse mode • Gate Value Status • Gate Event Interrupt Figure 18 block diagram of the Timer1 module ...
Page 160
... Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. Clock Source Instruction Clock (F /4) OSC System Clock (F ) OSC External Clocking on T1CKI Pin Secondary Oscillator Circuit on SOSCI/SOSCO Pins LFINTOSC Preliminary internal clock source is selected, the 2011 Microchip Technology Inc. ...
Page 161
... A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 18.6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry ...
Page 162
... TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). Preliminary 2011 Microchip Technology Inc. Figure 18-6 for ...
Page 163
... T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 18.9 ECCP/CCP Capture/Compare Time Base The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...
Page 164
... PIC16(L)F1516/7/8/9 FIGURE 18-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 18-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41452B-page 164 Preliminary 2011 Microchip Technology Inc ...
Page 165
... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41452B-page 165 ...
Page 166
... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41452B-page 166 Set by hardware on falling edge of T1GVAL Preliminary 2011 Microchip Technology Inc. Cleared by hardware on falling edge of T1GVAL Cleared by software ...
Page 167
... This bit is ignored. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 168
... Timer0 overflow output 10 = Timer2 Match PR2 11 = Reserved DS41452B-page 168 R/W-0/u R/W/HC-0/u R-x/x T1GSPM T1GGO/ T1GVAL DONE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HC = Bit is cleared by hardware Preliminary R/W-0/u R/W-0/u T1GSS<1:0> bit 0 2011 Microchip Technology Inc. ...
Page 169
... TRISC TRISC7 TRISC6 TMR1CS<1:0> T1CON TMR1GE T1GPOL T1GCON Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 ANSB3 ANSB2 DC1B<1:0> ...
Page 170
... PIC16(L)F1516/7/8/9 NOTES: DS41452B-page 170 Preliminary 2011 Microchip Technology Inc. ...
Page 171
... Optional use as the shift clock for the MSSP modules See Figure 19-1 for a block diagram of Timer2. FIGURE 19-1: TIMER2 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 T2CKPS<1:0> 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 TMR2 Output Reset TMR2 Postscaler Comparator 1 PR2 T2OUTPS<3:0> Preliminary ...
Page 172
... Synchronous Serial Port (MSSP) Module” 19.4 Timer2 Operation During Sleep Timer2 cannot be operated while the processor is in Sleep mode. The contents of the TMR2 and PR2 the output registers will remain unchanged while the processor is “Timer2 in Sleep mode. Preliminary Section 21.0 2011 Microchip Technology Inc. ...
Page 173
... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler Prescaler is 64 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 R/W-0/0 R/W-0/0 R/W-0/0 TMR2ON U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary ...
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... DC1B<1:0> DC2B<1:0> TMR0IE INTE IOCIE TMR0IF RCIE TXIE SSPIE CCP1IE RCIF TXIF SSPIF CCP1IF T2OUTPS<3:0> TMR2ON Preliminary Register Bit 1 Bit 0 on Page CCP1M<3:0> 184 CCP2M<3:0> 184 INTF IOCIF 80 TMR2IE TMR1IE 81 TMR2IF TMR1IF 83 171* T2CKPS<1:0> 173 171* 2011 Microchip Technology Inc. ...
Page 175
... CCPx module. Register names, module signals, I/O pins, and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module, when required. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 the same generic Preliminary ...
Page 176
... NEW_CAPT_PS ;Load the W reg with MOVWF CCPxCON CCPRxL TMR1L Preliminary demonstrates the code to CHANGING BETWEEN CAPTURE PRESCALERS ;Set Bank bits to point ;to CCPxCON ;Turn CCP module off ;the new prescaler ;move value and CCP ON ;Load CCPxCON with this ;value 2011 Microchip Technology Inc. ...
Page 177
... APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 “Alternate Pin Function” more information. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 for Preliminary DS41452B-page 177 ...
Page 178
... Special Event Trigger and the clock edge that generates preclude the Reset from occurring. Preliminary ) should not be used in Compare OSC /4) or from an OSC SPECIAL EVENT TRIGGER CCPx CCP2 for the match condition by the Timer1 Reset, will 2011 Microchip Technology Inc. ...
Page 179
... APFCON. To determine which pins can be moved and what their default locations are upon a Reset, see Section 12.1 “Alternate Pin Function” more information. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 is shut OSC for Preliminary ...
Page 180
... PR2 The 8-bit timer TMR2 register is concatenated Note 1: with the 2-bit internal system clock (F 2 bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPRxH is a read-only register. 2: Preliminary 2011 Microchip Technology Inc. TMR2 = PR2 CCPxCON<5:4> CCPx TRIS ), or OSC ...
Page 181
... Prescale Value 1/F Note 1: OSC OSC 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • ...
Page 182
... Preliminary log 4 PR2 + 1 ----------------------------------------- - bits 2 log = 20 MHz) 156.3 kHz 208.3 kHz 1 1 0x1F 0x17 7 6 MHz) 153.85 kHz 200.0 kHz 1 1 0x0C 0x09 5 5 2011 Microchip Technology Inc. ...
Page 183
... TRISA7 TRISA6 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 20.3.10 ALTERNATE PIN LOCATIONS This module incorporates I/O pins that can be moved to other locations with the use of the alternate pin function register APFCON ...
Page 184
... Compare mode: Special Event Trigger (sets CCPxIF bit (CCP2), starts A/D conversion if A/D module is enabled) 11xx = PWM mode DS41452B-page 184 R/W-0/0 R/W-0/0 R/W-0/0 DCxB<1:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Reset (1) Preliminary R/W-0/0 R/W-0/0 CCPxM<3:0> bit 0 2011 Microchip Technology Inc. ...
Page 185
... Slave Select Synchronization (Slave mode only) • Daisy-chain connection of slave devices Figure 21 block diagram of the SPI interface module. FIGURE 21-1: MSSP BLOCK DIAGRAM (SPI MODE) SDI SDO SS SCK 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 Data Bus Read Write SSPBUF Reg SSPSR Reg Shift bit 0 Clock SS Control ...
Page 186
... Start bit detect, Stop bit detect Write collision detect Set/Reset SSPSTAT, WCOL, SSPOV Clock arbitration Reset SEN, PEN (SSPCON2) State counter for Set SSPIF, BCLIF end of XMIT/RCV Address Match detect Preliminary [SSPM 3:0] Baud Rate Generator (SSPADD) 2011 Microchip Technology Inc. ...
Page 187
... FIGURE 21-3: MSSP BLOCK DIAGRAM (I SCL SDA 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 2 C™ SLAVE MODE) Internal Data Bus Read Write SSPBUF Reg Shift Clock SSPSR Reg MSb LSb SSPMSK Reg Match Detect Addr Match SSPADD Reg Set, Reset Start and ...
Page 188
... Every slave device connected to the bus that has not been selected through its slave select line must disre- gard the clock and transmission signals and must not transmit out any data of its own. Preliminary 2011 Microchip Technology Inc. ...
Page 189
... In receive operations, SSPSR and SSPBUF together create a buffered receiver. When SSPSR receives a complete byte transferred to SSPBUF and the SSPIF interrupt is set. During transmission, the SSPBUF is not buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 SCK SDI SDI SDO SS ...
Page 190
... SSPBUF register. Additionally, the SSPSTAT register indicates the various Status conditions. SPI Slave SSPM<3:0> = 010x SDO SDI Serial Input Buffer SDI SDO Shift Register MSb Serial Clock SCK SCK Slave Select SS (optional) Preliminary (SSPBUF) (SSPSR) LSb Processor 2 2011 Microchip Technology Inc. ...
Page 191
... Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 The clock polarity is selected by appropriately programming the CKP bit of the SSPCON1 register and the CKE bit of the SSPSTAT register. This then, would give waveforms for SPI communication as Figure ...
Page 192
... SMP bit of the SSPSTAT register must remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. Preliminary enabled (SSPCON1<3:0> 2011 Microchip Technology Inc. ...
Page 193
... CKE = 0) Write to SSPBUF SSPBUF to SSPSR SDO bit 7 SDI bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 SCK SDI SDI SDO SS SCK SDI SDO SS SCK SDI SDO SS Shift register SSPSR and bit count are reset ...
Page 194
... SSPBUF Valid SDO bit 7 SDI bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPBUF Write Collision detection active DS41452B-page 194 bit 6 bit 2 bit 5 bit 4 bit 3 bit 6 bit 3 bit 2 bit 5 bit 4 Preliminary bit 1 bit 0 bit 0 bit 1 bit 0 bit 0 2011 Microchip Technology Inc. ...
Page 195
... Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Legend: * Page provides register information. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmis- sion/reception will remain in that state until the device wakes ...
Page 196
... Single message where a master writes data to a slave. • Single message where a master reads data from a slave. • Combined message where a master initiates a minimum of two writes, or two reads combination of writes and reads, to one or more slaves. Preliminary 2011 Microchip Technology Inc. SCL Slave SDA ...
Page 197
... Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 21.3.2 ARBITRATION Each master device must monitor the bus for Start and Stop bits ...
Page 198
... Slave. This data is the next and all following bytes until a Restart or Stop. SCL low to stall communication. Any time the SDA line is sampled low by the module while it is out- putting and expected high state. 2011 Microchip Technology Inc. ...
Page 199
... S Start Condition 2 FIGURE 21-13 RESTART CONDITION 2011 Microchip Technology Inc. PIC16(L)F1516/7/8/9 21.4.7 RESTART CONDITION A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, ...
Page 200
... This is only valid for a slave after it has received a complete high and low address byte match. Preliminary (Register 21-6) contains the (Register 21-5) affects the Section 21.5.9 “SSP 2011 Microchip Technology Inc. ...