PIC16F1823-I/SL Microchip Technology, PIC16F1823-I/SL Datasheet - Page 275

• Manufacturer Part Number: PIC16F1823-I/SL
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 12 I/0, Enhanced Mid Range Core 14
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1823-I/SL

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Core: PIC
• Processor Series: PIC16F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 32 MHz
• Data Ram Size: 128 B
• On-chip Adc: Yes
• Number Of Programmable I/os: 12
• Number Of Timers: 3
• Operating Supply Voltage: 2.3 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Height: 1.25 mm
• Interface Type: I2C, SPI, USART
• Length: 8.65 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.3 V
• Width: 3.9 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 25-34:
FIGURE 25-35:
 2010 Microchip Technology Inc.
SDA
SCL
SEN
S
BCL1IF
SSP1IF
S
BCL1IF
SSP1IF
SDA
SCL
SEN
BUS COLLISION DURING START CONDITION (SCL = 0)
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA pulled low by other master.
Reset BRG and assert SDA.
’0’
’0’
SCL = 0 before BRG time-out,
bus collision occurs. Set BCL1IF.
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
Less than T
PIC12F/LF1822/PIC16F/LF1823
BRG
SDA = 0, SCL = 1
SDA = 0, SCL = 1
Preliminary
SDA = 0, SCL = 1,
set SSP1IF
T
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BRG
S
Set S
T
BRG
T
BRG
Set SSP1IF
SCL = 0 before SDA = 0,
bus collision occurs. Set BCL1IF.
SCL pulled low after BRG
time-out
Interrupt cleared
by software
Interrupts cleared
by software
’0’
’0’
’0’
DS41413B-page 275