PIC16F1823-I/SL Microchip Technology, PIC16F1823-I/SL Datasheet - Page 289

• Manufacturer Part Number: PIC16F1823-I/SL
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 12 I/0, Enhanced Mid Range Core 14
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1823-I/SL

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Core: PIC
• Processor Series: PIC16F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 32 MHz
• Data Ram Size: 128 B
• On-chip Adc: Yes
• Number Of Programmable I/os: 12
• Number Of Timers: 3
• Operating Supply Voltage: 2.3 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• A/d Bit Size: 10 bit
• A/d Channels Available: 8
• Height: 1.25 mm
• Interface Type: I2C, SPI, USART
• Length: 8.65 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.3 V
• Width: 3.9 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 26-1:
 2010 Microchip Technology Inc.
BAUDCON
INTCON
PIE1
PIR1
RCSTA
SPBRGL
SPBRGH
TRISA
TRISC
TXREG
TXSTA
Legend:
Note 1:
Name
(2)
2:
*
— = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Transmission.
Page provides register information.
PIC12F/LF1822 only.
PIC16F/LF1823 only.
EUSART Transmit Data Register
TMR1GIE
TMR1GIF
ABDOVF
CSRC
SPEN
SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
GIE
—
—
RCIDL
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
—
—
PIC12F/LF1822/PIC16F/LF1823
TRISA5
TMR0IE
TRISC5
SREN
TXEN
RCIE
RCIF
Bit 5
—
(1)
TRISA4
TRISC4
Preliminary
CREN
SYNC
SCKP
Bit 4
INTE
TXIE
TXIF
BRG<15:8>
BRG<7:0>
(1)
TRISC3
ADDEN
TRISA3
SENDB
BRG16
SSPIE
SSPIF
IOCIE
Bit 3
TMR0IF
CCP1IE
CCP1IF
TRISC2
TRISA2
BRGH
FERR
Bit 2
—
TMR2IE
TMR2IF
TRISA1
TRISC1
OERR
TRMT
WUE
Bit 1
INTF
TMR1IE
TMR1IF
TRISC0
ABDEN
TRISA0
IOCIF
RX9D
TX9D
Bit 0
DS41413B-page 289
Register on
Page
297*
297*
287*
296
101
102
105
295
124
128
294