PIC16F707-I/MV Microchip Technology, PIC16F707-I/MV Datasheet - Page 169
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PIC16F707-I/MV
Manufacturer Part Number
PIC16F707-I/MV
Description
14KB Flash Program, MTouch, 32ch CSM, 1.8V-5.5V, 16MHz Internal Oscillator, 8b A
Manufacturer
Microchip Technology
Series
PIC® XLP™ mTouch™ 16Fr
Datasheet
1.PIC16F707-IPT.pdf
(284 pages)
Specifications of PIC16F707-I/MV
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
363 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-UFQFN Exposed Pad
Processor Series
PIC16F
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 169 of 284
- Download datasheet (3Mb)
19.2.4
Once the SSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock line (SCL).
19.2.4.1
In 7-bit Addressing mode (Figure 19-10), the value of
register SSPSR<7:1> is compared to the value of
register SSPADD<7:1>. The address is compared on
the falling edge of the eighth clock (SCL) pulse. If the
addresses match, and the BF and SSPOV bits are
clear, the following events occur:
• The SSPSR register value is loaded into the
• The BF bit is set.
• An ACK pulse is generated.
• SSP interrupt flag bit, SSPIF of the PIR1 register,
19.2.4.2
In 10-bit Address mode, two address bytes need to be
received by the slave (Figure 19-11). The five Most Sig-
nificant bits (MSbs) of the first address byte specify if it
is a 10-bit address. The R/W bit of the SSPSTAT regis-
ter must specify a write so the slave device will receive
the second address byte. For a 10-bit address, the first
byte would equal ‘1111 0 A9 A8 0’, where A9 and
A8 are the two MSbs of the address.
2010 Microchip Technology Inc.
SSPBUF register.
is set (interrupt is generated if enabled) on the
falling edge of the ninth SCL pulse.
ADDRESSING
7-bit Addressing
10-bit Addressing
Preliminary
PIC16F707/PIC16LF707
The sequence of events for 10-bit address is as follows
for reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
If data is requested by the master, once the slave has
been addressed:
1.
2.
3.
4.
5.
19.2.4.3
The Address Masking register (SSPMSK) is only
accessible while the SSPM bits of the SSPCON
register are set to ‘1001’. In this register, the user can
select which bits of a received address the hardware
will compare when determining an address match. Any
bit that is set to a zero in the SSPMSK register, the
corresponding bit in the received address byte and
SSPADD register are ignored when determining an
address match. By default, the register is set to all
ones, requiring a complete match of a 7-bit address or
the lower eight bits of a 10-bit address.
Load SSPADD register with high byte of address.
Receive first (high) byte of address (bits SSPIF,
BF and UA of the SSPSTAT register are set).
Read the SSPBUF register (clears bit BF).
Clear the SSPIF flag bit.
Update the SSPADD register with second (low)
byte of address (clears UA bit and releases the
SCL line).
Receive low byte of address (bits SSPIF, BF and
UA are set).
Update the SSPADD register with the high byte
of address. If match releases SCL line, this will
clear bit UA.
Read the SSPBUF register (clears bit BF).
Clear flag bit SSPIF.
Receive repeated Start condition.
Receive repeat of high byte address with R/W = 1,
indicating a read.
BF bit is set and the CKP bit is cleared, stopping
SCL and indicating a read request.
SSPBUF is written, setting BF, with the data to
send to the master device.
CKP is set in software, releasing the SCL line.
Address Masking
DS41418A-page 169
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