PIC16F707-I/MV Microchip Technology, PIC16F707-I/MV Datasheet - Page 179
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC16F707-I/MV
Manufacturer Part Number
PIC16F707-I/MV
Description
14KB Flash Program, MTouch, 32ch CSM, 1.8V-5.5V, 16MHz Internal Oscillator, 8b A
Manufacturer
Microchip Technology
Series
PIC® XLP™ mTouch™ 16Fr
Datasheet
1.PIC16F707-IPT.pdf
(284 pages)
Specifications of PIC16F707-I/MV
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
363 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-UFQFN Exposed Pad
Processor Series
PIC16F
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 179 of 284
- Download datasheet (3Mb)
20.0
The Flash program memory is readable during normal
operation over the full V
data from Program Memory, five Special Function
Registers (SFRs) are used:
• PMCON1
• PMDATL
• PMDATH
• PMADRL
• PMADRH
EXAMPLE 20-1:
2010 Microchip Technology Inc.
PROGRAM MEMORY READ
BANKSEL PMADRL
MOVF
MOVWF
MOVF
MOVWF
BANKSEL PMCON1
BSF
NOP
NOP
BANKSEL PMDATL
MOVF
MOVWF
MOVF
MOVWF
PROGRAM MEMORY READ
MS_PROG_ADDR, W ;
PMADRH
LS_PROG_ADDR, W ;
PMADRL
PMCON1, RD
PMDATL, W
LOWPMBYTE
PMDATH, W
HIGHPMBYTE
DD
range of the device. To read
;
;MS Byte of Program Address to read
;LS Byte of Program Address to read
;
;Initiate Read
;Any instructions here are ignored as program
;memory is read in second cycle after BSF
;
;W = LS Byte of Program Memory Read
;
;W = MS Byte of Program Memory Read
;
Preliminary
PIC16F707/PIC16LF707
The value written to the PMADRH:PMADRL register
pair determines which program memory location is
read. The read operation will be initiated by setting the
RD bit of the PMCON1 register. The program memory
flash controller takes two instructions to complete the
read. As a consequence, after the RD bit has been set,
the next two instructions will be ignored. To avoid
conflict with program execution, it is recommended that
the two instructions following the setting of the RD bit
are NOP. When the read completes, the result is placed
in the PMDATLH:PMDATL register pair. Refer to
Example 20-1 for sample code.
Note:
Code-protect does not effect the CPU
from performing a read operation on the
program memory. For more information,
refer to Section 8.2 “Code Protection”
DS41418A-page 179
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