PIC16LF1847T-I/SO Microchip Technology, PIC16LF1847T-I/SO Datasheet - Page 263

• Manufacturer Part Number: PIC16LF1847T-I/SO
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ mTouch™ 16Fr

Specifications of PIC16LF1847T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (0.295", 7.50mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.5.8 GENERAL CALL ADDRESS SUPPORT
The addressing procedure for the I
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the
master device. The exception is the general call
address which can address all devices. When this
address is used, all devices should, in theory, respond
with an acknowledge.
The general call address is a reserved address in the
I
GCEN bit of the SSPxCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPxADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software
Figure 25-23
sequence.
FIGURE 25-24:
25.5.9 SSPX MASK REGISTER
An SSPx Mask (SSPxMSK) register
available in I
held in the SSPxSR register during an address
comparison operation. A zero (‘0’) bit in the SSPxMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSPx operation until written with a mask value.
The SSPx Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
 2011 Microchip Technology Inc.
2
C protocol, defined as address 0x00. When the
only. The SSPx mask has no effect during the
reception of the first (high) byte of the address.
GCEN (SSPxCON2<7>)
SDAx
SCLx
SSPxIF
BF (SSPxSTAT<0>)
can
2
C Slave mode as a mask for the value
shows
read
S
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
a
SSPxBUF
1
general
2
General Call Address
2
3
C bus is such that
(Register
and
call
4
reception
5
respond.
25-5) is
6
Preliminary
7
R/W =
8
0
ACK
In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
it would in 7-bit mode.
If the AHEN bit of the SSPxCON3 register is set, just
as with any other address reception, the slave hard-
ware will stretch the clock after the 8th falling edge of
SCLx. The slave must then set its ACKDT value and
release the clock with communication progressing as it
would normally.
Address is compared to General Call Address
after ACK, set interrupt
9
D7
1
D6
2
Cleared by software
SSPxBUF is read
Receiving Data
D5
3
PIC16(L)F1847
D4
4
D3
5
D2
6
D1
7
DS41453B-page 263
D0
8
ACK
9
’1’