PIC18F25K80-E/SO Microchip Technology, PIC18F25K80-E/SO Datasheet - Page 232
![ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SOIC .300in TUBE](/photos/16/11/161109/soic-28_sml.jpg)
PIC18F25K80-E/SO
Manufacturer Part Number
PIC18F25K80-E/SO
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F25K80-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC18F25K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F66K80 FAMILY
16.2
Timer3 can operate in these modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
• Timer with Gated Control
FIGURE 16-1:
DS39977C-page 232
Note 1:
T1CON.SOSCEN
T3CON.SOSCEN
SCS<1:0> = 01
T3G
From TMR4
Match PR4
From Comparator 1
Output
From Comparator 2
Output
Timer3 Operation
2:
3:
4:
T3GSS<1:0>
SOSCGO
SOSCO/SCLKI
ST Buffer is high-speed type when using T3CKI.
Timer3 registers increment on rising edge.
Synchronization does not operate while in Sleep.
The output of SOSC is determined by the SOSCSEL<1:0> Configuration bits.
T3GPOL
SOSCI
T3CKI
Set Flag bit,
TMR3IF, on
Overflow
TIMER3 BLOCK DIAGRAM
00
10
11
01
TMR3ON
T3GTM
TMR3H
SOSC
EN
OUT
TMR3
(1)
T3G_IN
(4)
(2)
D
R
CK
TMR3L
Q
Q
1
0
Preliminary
TMR3CS<1:0>
0
1
T3GGO/T3DONE
Q
Internal
Internal
F
OSC
Clock
Clock
F
OSC
EN
/4
D
external clock from the T3CKI pin (on the rising edge
The operating mode is determined by the clock select
bits, TMR3CSx (T3CON<7:6>). When the TMR3CSx bits
are cleared (= 00 ), Timer3 increments on every internal
instruction cycle (F
Timer3 clock source is the system clock (F
when it is ‘ 10 ’, Timer3 works as a counter from the
after the first falling edge) or the SOSC oscillator.
Single Pulse
Acq. Control
T3CLK
10
01
00
T3GSPM
T3CKPS<1:0>
T3SYNC
Prescaler
1, 2, 4, 8
TMR3ON
0
1
2
0
1
OSC
Internal
F
OSC
Clock
T3GVAL
/4). When TMR3CSx = 01 , the
TMR3GE
/2
2011 Microchip Technology Inc.
Q1
Synchronized
Synchronize
Interrupt
Clock Input
D
EN
det
det
Sleep Input
Q
(3)
Set
TMR3GIF
Data Bus
RD
T3GCON
OSC
), and
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