PIC18F25K80-E/SO Microchip Technology, PIC18F25K80-E/SO Datasheet - Page 82
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PIC18F25K80-E/SO
Manufacturer Part Number
PIC18F25K80-E/SO
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F25K80-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC18F25K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F66K80 FAMILY
REGISTER 5-1:
DS39977C-page 82
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
R/W-0
IPEN
2:
2: Brown-out Reset is said to have occurred when BOR is ‘ 0 ’ and POR is ‘ 1 ’ (assuming that POR was set to
If SBOREN is enabled, its Reset state is ‘ 1 ’; otherwise, it is ‘ 0 ’.
The actual Reset value of POR is determined by the type of device Reset. See the notes following this
register and
Power-on Resets may be detected.
‘ 1 ’ by software immediately after a Power-on Reset).
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
SBOREN: BOR Software Enable bit
If BOREN<1:0> = 01 :
1 = BOR is enabled
0 = BOR is disabled
If BOREN<1:0> = 00 , 10 or 11 :
Bit is disabled and reads as ‘ 0 ’.
CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has not occurred.
0 = A Configuration Mismatch Reset occurred. Must be set in software once the Reset occurs.
RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after a
TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
PD: Power-down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
SBOREN
R/W-1
Brown-out Reset occurs)
RCON: RESET CONTROL REGISTER
Section 5.7 “Reset State of Registers”
(1)
W = Writable bit
‘1’ = Bit is set
R/W-1
CM
R/W-1
(2)
Preliminary
RI
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-1
TO
for additional information.
R-1
PD
2011 Microchip Technology Inc.
x = Bit is unknown
R/W-0
POR
(2)
R/W-0
BOR
bit 0
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