PIC18F25K80-E/SO Microchip Technology, PIC18F25K80-E/SO Datasheet - Page 84
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PIC18F25K80-E/SO
Manufacturer Part Number
PIC18F25K80-E/SO
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F25K80-E/SO
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Processor Series
PIC18F25K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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The BOR accuracy varies with its power level. The lower
PIC18F66K80 FAMILY
5.4
The PIC18F66K80 family has four BOR Power modes:
• High-Power BOR
• Medium Power BOR
• Low-Power BOR
• Zero-Power BOR
Each power mode is selected by the BORPWR<1:0>
setting (CONFIG2L<6:5>). For low, medium and
high-power BOR, the module monitors the V
ing on the BORV<1:0> setting (CONFIG1L<3:2>). The
typical current draw ( IBOR) for zero, low and medium
power BOR is 200 nA, 750 nA and 3 A, respectively. A
BOR event re-arms the Power-on Reset. It also causes
a Reset, depending on which of the trip levels has been
set: 1.8V, 2V, 2.7V or 3V.
BOR is enabled by BOREN<1:0> (CONFIG2L<2:1>)
and the SBOREN bit (RCON<6>). The four BOR
configurations are summarized in
In Zero-Power BOR (ZPBORMV), the module monitors
the V
ZPBORMV does not cause a Reset, but re-arms the
POR.
the power setting, the less accurate the BOR trip levels
are. Therefore, the high-power BOR has the highest
accuracy and the low-power BOR has the lowest accu-
racy. The trip levels (B
consumption (
Power-Down and Supply Current PIC18F66K80
Family (Industrial/Extended)”
below B
Section 31.0 “Electrical Characteristics”
5.4.1
When BOREN<1:0> = 01 , the BOR can be enabled or
disabled by the user in software. This is done with the
control bit, SBOREN (RCON<6>). Setting SBOREN
enables the BOR to function as previously described.
Clearing SBOREN disables the BOR entirely. The
SBOREN bit operates only in this mode; otherwise it is
read as ‘ 0 ’.
TABLE 5-1:
DS39977C-page 84
BOREN1
BOR Configuration
DD
0
0
1
1
VDD
Brown-out Reset (BOR)
voltage and re-arms the POR at about 2V.
SOFTWARE ENABLED BOR
(TBOR, Parameter 35) can all be found in
Section 31.2 “DC Characteristics:
BOREN0
BOR CONFIGURATIONS
0
1
0
1
VDD
, Parameter D005), current
(RCON<6>)
Unavailable
Unavailable
Unavailable
SBOREN
Available
Status of
) and time required
Table
5-1.
.
DD
BOR disabled; must be enabled by reprogramming the Configuration bits.
BOR enabled in software; operation controlled by SBOREN.
BOR enabled in hardware in Run and Idle modes; disabled during Sleep
mode.
BOR enabled in hardware; must be disabled by reprogramming the
Configuration bits.
depend-
Preliminary
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change BOR configuration. It also allows the user to
tailor device power consumption in software by elimi-
nating the incremental current that the BOR consumes.
While the BOR current is typically very small, it may
have some impact in low-power applications.
5.4.2
When Brown-out Reset is enabled, the BOR bit always
resets to ‘ 0 ’ on any Brown-out Reset or Power-on
Reset event. This makes it difficult to determine if a
Brown-out Reset event has occurred just by reading
the state of BOR alone. A more reliable method is to
simultaneously check the state of both POR and BOR.
This assumes that the POR bit is reset to ‘ 1 ’ in software
immediately after any Power-on Reset event. IF BOR
is ‘ 0 ’ while POR is ‘ 1 ’, it can be reliably assumed that a
Brown-out Reset event has occurred.
5.4.3
When BOREN<1:0> = 10 , the BOR remains under
hardware
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When the
device returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
Note:
BOR Operation
Even when BOR is under software con-
trol, the Brown-out Reset voltage level is
still set by the BORV<1:0> Configuration
bits; it cannot be changed in software.
DETECTING BOR
DISABLING BOR IN SLEEP MODE
control
and
2011 Microchip Technology Inc.
operates
as
previously
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