PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 102
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PIC18F27J53T-I/SO
Manufacturer Part Number
PIC18F27J53T-I/SO
Description
28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F27J53T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (6Mb)
PIC18F47J53 FAMILY
6.3.6
The STATUS register, shown in Register 6-2, contains
the arithmetic status of the ALU. The STATUS register
can be the operand for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV or N bits,
then the write to these five bits is disabled.
These bits are set or cleared according to the device
logic. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended. For example, CLRF STATUS will set the Z bit
but leave the other bits unchanged. The STATUS
REGISTER 6-2:
DS39964B-page 102
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
—
2:
For Digit Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source
register.
For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the sec-
ond operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of
the source register.
STATUS REGISTER
Unimplemented: Read as ‘0’
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative
(ALU MSB = 1).
1 = Result was negative
0 = Result was positive
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude,
which causes the sign bit (bit 7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Digit Borrow bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry out from the 4
0 = No carry out from the 4
C: Carry/Borrow bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry out from the MSb of the result occurred
0 = No carry out from the MSb of the result occurred
U-0
—
STATUS REGISTER (ACCESS FDBh)
W = Writable bit
‘1’ = Bit is set
(2)
U-0
—
th
th
low-order bit of the result occurred
low-order bit of the result
(1)
R/W-x
N
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-x
register then reads back as ‘000u u1uu’. It is recom-
mended, therefore, that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the STATUS
register because these instructions do not affect the Z,
C, DC, OV or N bits in the STATUS register.
For other instructions not affecting any Status bits, see
the instruction set summary in Table 29-2 and
Table 29-3.
OV
Note:
The C and DC bits operate as Borrow and
Digit
subtraction.
R/W-x
Z
Borrow
2010 Microchip Technology Inc.
x = Bit is unknown
R/W-x
DC
bits,
(1)
respectively
R/W-x
C
(2)
bit 0
in
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