PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 136
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PIC18F27J53T-I/SO
Manufacturer Part Number
PIC18F27J53T-I/SO
Description
28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F27J53T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 136 of 586
- Download datasheet (6Mb)
PIC18F47J53 FAMILY
REGISTER 9-15:
DS39964B-page 136
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OSCFIP
R/W-1
OSCFIP: Oscillator Fail Interrupt Priority bit
1 = High priority
0 = Low priority
CM2IP: Comparator 2 Interrupt Priority bit
1 = High priority
0 = Low priority
C12IP: Comparator 1 Interrupt Priority bit
1 = High priority
0 = Low priority
USBIP: USB Interrupt Priority bit
1 = High priority
0 = Low priority
BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module)
1 = High priority
0 = Low priority
HLVDIP: High/Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
CCP2IP: ECCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
CM2IP
R/W-1
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (ACCESS FA2h)
W = Writable bit
‘1’ = Bit is set
CM1IP
R/W-1
USBIP
R/W-1
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
BCL1IP
R/W-1
HLVDIP
R/W-1
2010 Microchip Technology Inc.
x = Bit is unknown
TMR3IP
R/W-1
CCP2IP
R/W-1
bit 0
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