PIC18F27J53T-I/SO Microchip Technology, PIC18F27J53T-I/SO Datasheet - Page 183
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PIC18F27J53T-I/SO
Manufacturer Part Number
PIC18F27J53T-I/SO
Description
28-pin, USB, 128KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 28 SOIC .30
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F27J53T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 183 of 586
- Download datasheet (6Mb)
REGISTER 11-4:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-2
bit 1-0
Note 1:
WAITB1
R/W-0
2:
(2)
This register is only available on 44-pin devices.
WAITBx and WAITEx bits are ignored whenever WAITM<3:0> = 0000.
WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits
11 = Data Wait of 4 T
10 = Data Wait of 3 T
01 = Data Wait of 2 T
00 = Data Wait of 1 T
WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits
1111 = Wait of additional 15 T
.
.
.
0001 = Wait of additional 1 T
0000 = No additional Wait cycles (operation forced into one T
WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits
11 = Wait of 4 T
10 = Wait of 3 T
01 = Wait of 2 T
00 = Wait of 1 T
WAITB0
R/W-0
PMMODEL: PARALLEL PORT MODE REGISTER LOW BYTE (BANKED F5Ch)
(2)
W = Writable bit
‘1’ = Bit is set
CY
CY
CY
CY
WAITM3
R/W-0
CY
CY
CY
CY
; multiplexed address phase of 4 T
; multiplexed address phase of 3 T
; multiplexed address phase of 2 T
; multiplexed address phase of 1 T
CY
CY
WAITM2
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F47J53 FAMILY
WAITM1
R/W-0
CY
CY
CY
CY
WAITM0
CY
R/W-0
)
(2)
(2)
x = Bit is unknown
WAITE1
R/W-0
(2)
DS39964B-page 183
WAITE0
R/W-0
bit 0
(2)
(1)
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