PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 105

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

8.6.3
Figure 8-3 shows an example of 16-Bit Byte Select
mode. This mode allows table write operations to
word-wide external memories with byte selection
capability. This generally includes both word-wide
Flash and SRAM devices.
During a TBLWT cycle, the TABLAT data is presented
on the upper and lower byte of the AD<15:0> bus. The
WRH signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written, based on the Least
Significant bit of the TBLPTR register.
FIGURE 8-3:
 2010 Microchip Technology Inc.
Note 1:
PIC18F85J11
2:
3:
16-BIT BYTE SELECT MODE
A<19:16>
AD<15:8>
This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”.
The upper order address lines are used only for 20-bit address width.
Demultiplexing is only required when multiple memory devices are accessed.
AD<7:0>
WRH
WRL
ALE
BA0
OE
UB
I/O
LB
(2)
16-BIT BYTE SELECT MODE EXAMPLE
373
373
A<20:1>
A<20:1>
PIC18F85J11 FAMILY
138
Flash and SRAM devices use different control signal
combinations to implement Byte Select mode. JEDEC
standard Flash memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard static RAM memories, on the other hand, use
the UB or LB signals to select the byte.
(3)
A<x:1>
A<x:1>
CE
UB
A0
CE
BYTE/WORD
LB
OE
FLASH Memory
SRAM Memory
Address Bus
Data Bus
Control Lines
WR
JEDEC Word
JEDEC Word
OE WR
(1)
D<15:0>
D<15:0>
DS39774D-page 105
(1)
D<15:0>
D<15:0>