PIC18F64J11T-I/PT Microchip Technology, PIC18F64J11T-I/PT Datasheet - Page 169

• Manufacturer Part Number: PIC18F64J11T-I/PT
• Description: 16KB, Flash, 1024bytes-RAM, 51I/O, 8-bit Family,nanoWatt 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F64J11T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18F64J11T-I/PTTR

16.0
PIC18F85J11
(Capture/Compare/PWM) modules, designated CCP1
and CCP2. Both modules implement standard Capture,
Compare and Pulse-Width Modulation (PWM) modes.
REGISTER 16-1:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
bit 3-0
Note 1:
U-0
—
CAPTURE/COMPARE/PWM
(CCP) MODULES
CCPxM<3:0> = 1011 will only reset the timer and not start an A/D conversion on CCPx match.
Unimplemented: Read as ‘0’
DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCPx Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight
Most Significant bits (DCx9:DCx2) of the duty cycle are found in CCPRxL.
CCPxM<3:0>: CCPx Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit
1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin
1011 = Compare mode: Special Event Trigger; reset timer; start A/D conversion on CCPx match
11xx = PWM mode
family
U-0
—
CCPxCON: CCPx CONTROL REGISTER (CCP1, CCP2 MODULES)
is set)
is set)
reflects I/O state)
(CCPxIF bit is set)
devices
W = Writable bit
‘1’ = Bit is set
DCxB1
R/W-0
have
(1)
two
DCxB0
R/W-0
CCP
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CCPxM3
PIC18F85J11 FAMILY
R/W-0
Each CCP module contains a 16-bit register which can
operate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
For the sake of clarity, all CCP module operation in the
following sections is described with respect to CCP2,
but is equally applicable to CCP1.
CCPxM2
R/W-0
x = Bit is unknown
CCPxM1
R/W-0
DS39774D-page 169
CCPxM0
R/W-0
bit 0