PIC18F65K90T-I/PT Microchip Technology, PIC18F65K90T-I/PT Datasheet - Page 247

• Manufacturer Part Number: PIC18F65K90T-I/PT
• Description: 32kB Flash, 2kB RAM, 1kB EE, NanoWatt XLP, LCD 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K90T-I/PT

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Details

TABLE 18-5:
18.4
In Pulse-Width Modulation (PWM) mode, the CCP4 pin
produces up to a 10-bit resolution PWM output. Since
the CCP4 pin is multiplexed with a PORTC or PORTE
data latch, the appropriate TRIS bit must be cleared to
make the CCP4 pin an output.
Figure 18-3
ECCP1 module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see
“Setup for PWM
 2009-2011 Microchip Technology Inc.
CCP6CON
CCP7CON
CCP8CON
CCP9CON
CCP10CON
CCPTMRS1
CCPTMRS2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1/3/5/7.
Note 1:
Note:
Name
2:
PWM Mode
(1)
Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90).
Unimplemented in 64-pin devices.
Clearing the CCP4CON register will force
the RC1 or RE7 output latch (depending
on device configuration) to the default low
level. This is not the PORTC or PORTE
I/O data latch.
(1)
shows a simplified block diagram of the
C7TSEL1
Operation”.
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1/3/5/7 (CONTINUED)
Bit 7
—
—
—
—
—
—
C7TSEL0
Bit 6
—
—
—
—
—
—
Section 18.4.3
DC10B1
DC6B1
DC7B1
DC8B1
DC9B1
Bit 5
—
—
C10TSEL0
C6TSEL0
DC10B0
DC6B0
DC7B0
DC8B0
DC9B0
Bit 4
PIC18F87K90 FAMILY
FIGURE 18-3:
CCP10M3 CCP10M2 CCP10M1 CCP10M0
CCP6M3
CCP7M3
CCP8M3
CCP9M3
Note 1:
CCPR4H (Slave)
Bit 3
—
—
Duty Cycle Registers
Comparator
CCPR4L
2:
TMR2
PR2
Comparator
The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
CCP4 and its appropriate timers are used as an
example. For details on all of the CCP modules and
their timer assignments, see
Table
C5TSEL0 C4TSEL1 C4TSEL0
C9TSEL0 C8TSEL1 C8TSEL0
CCP6M2
CCP7M2
CCP8M2
CCP9M2
Bit 2
18-3.
(Note 2)
(Note 2)
(Note 1)
Clear Timer,
ECCP1 Pin and
Latch D.C.
SIMPLIFIED PWM BLOCK
DIAGRAM
CCP6M1
CCP7M1
CCP8M1
CCP9M1
Bit 1
CCP4CON<5:4>
R
S
Table 18-2
DS39957D-page 247
CCP6M0
CCP7M0
CCP8M0
CCP9M0
Q
Bit 0
TRISC<2>
and
RC2/ECCP1
on Page:
Values
Reset
82
82
80
80
81
81
81