PIC24F16KA101T-I/SS Microchip Technology, PIC24F16KA101T-I/SS Datasheet - Page 5

• Manufacturer Part Number: PIC24F16KA101T-I/SS
• Description: 16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 16 I/O,16-bit PIC24F Family, NanoWatt
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F16KA101T-I/SS

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 16KB (5.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8. Module: I/O Ports (PORTA and PORTB)
 2010 Microchip Technology Inc.
The functions associated with port pins, RB0
and RA0, may be interconnected in unexpected
ways.
PORTB pin, RB0, may not operate correctly as
an input if the SPI module is enabled
(SPI1CON<15> = 1). Additionally, the pull-up,
pull-down and the Change Notification (CN4)
functionality are disabled. RB0 does operate
correctly with the SPI enabled if it is configured
as an output.
PORTA pin, RA0, may not operate correctly as
an input when the open-drain output is enabled
for RB0 (ODCB<0>). RA0 will operate correctly
as an output.
However, when the analog input on RB0 (AN2)
is enabled (AD1PCFG<2> = 0) and the SPI
module is enabled, RB0 will be driven as a
digital output, not as a analog input.
Work around
To enable RB0 as a digital input, enable the
open-drain output for RB0 (ODCB<0>) and set
the latch bit (LATB<0> = 1). The Change Notifi-
cation (CN4), pull-up and pull-down for this pin
will function correctly as well.
This work around may cause RA0 to function
incorrectly. There is no known work around for
RA0 as an input and RB0 with the open-drain
output enabled.
To enable RB0 as an analog input when SPI is
enabled:
1.
2.
3.
4.
Affected Silicon Revisions
A5
X
Enable the open-drain output for RB0
(ODCB<0>).
Set the latch bit (LATB<0> = 1).
Clear TRISB<0>.
Clear AD1PCFG<2>.
A6
X
A7
X
B0
PIC24F16KA102 FAMILY
9. Module: I/O Ports (PORTA and PORTB)
10. Module: Core (Low-Power BOR)
Note:
On 20-pin devices of the PIC24F16KA102 family,
the functions associated with port pins, RB2 and
RA2, may be interconnected in unexpected
ways.
PORTB pin, RB2, may not operate correctly as a
digital I/O if the analog input on PORTA pin, RA2
(AN4), is enabled (AD1PCFG<4> = 0). Both the
digital
multiplexed to RB2, are disabled.
Although this issue is similar in form to silicon
issue 8, it appears to be independent in its root
cause.
Work around
None.
Affected Silicon Revisions
When
(FPOR<6:5> = 00), BOR events may result in a
device Reset in which both the BOR and POR
bits are set.
This differs from the expected behavior of simply
re-arming the POR circuit to ensure that a POR
occurs when V
Work around
None.
Affected Silicon Revisions
A5
A5
X
X
This issue occurs in PIC24FXXKA101
(20-pin) devices only.
A6
A6
port,
the
X
X
A7
Low-Power
DD
A7
X
X
and
drops below the POR threshold.
B0
B0
the
U1RX
BOR
DS80473F-page 5
is
functionality
enabled