PIC24F16KA101T-I/SS Microchip Technology, PIC24F16KA101T-I/SS Datasheet - Page 6
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PIC24F16KA101T-I/SS
Manufacturer Part Number
PIC24F16KA101T-I/SS
Description
16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 16 I/O,16-bit PIC24F Family, NanoWatt
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.MA240017.pdf
(254 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F16KA101-ISS.pdf
(18 pages)
Specifications of PIC24F16KA101T-I/SS
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
16KB (5.5K x 24)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24F16KA101T-I/SS
Manufacturer:
MICROCHIR
Quantity:
20 000
PIC24F16KA102 FAMILY
11. Module: Comparator (I/O Pins)
12. Module: Comparator
DS80473F-page 6
Certain I/O pins may not function correctly as
digital inputs or outputs after specific comparator
outputs have been enabled with the COE bit
(CMxCON<14> = 1). These are:
•
•
This condition may continue even after the com-
parator in question has been disabled, using the
corresponding CON bit (CMxCON<15> = 0).
Work around
In addition to clearing the CON bit, also clear the
COE bit.
Affected Silicon Revisions
When a comparator is programmed to trig-
ger
(CMxCON<7:6> = 10 or 01), setting the CPOL
bit
comparator to flag the opposite edge-detect
event (e.g., a high-to-low edge instead of the
programmed low-to-high).
Work around
Leave CPOL = 0. In addition, use the opposite
setting of CMxCON<7:6> to achieve the correct
response (e.g., use ‘10’ for ‘01’).
Affected Silicon Revisions
A5
A5
X
X
RB14 (with Comparator 1)
RA6 (with Comparator 2)
(CMxCON<13> = 1)
on
A6
A6
X
X
certain
A7
A7
X
X
B0
B0
X
X
edge-detect
may
cause
events
the
13. Module: Core (Doze Mode)
Operations that immediately follow any manipu-
lations of the DOZE<2:0> or DOZEN bits
(CLDIV<14:11>) may not execute properly. In
particular, for instructions that operate on an
SFR, data may not be read properly. Also, bits
automatically cleared in hardware may not be
cleared if the operation occurs during this
interval.
Work around
Always insert a NOP instruction before and after
either of the following:
•
•
Affected Silicon Revisions
A5
X
Enabling or disabling Doze mode by setting
or clearing the DOZEN bit
Before or after changing the DOZE<2:0> bits
A6
X
A7
X
2010 Microchip Technology Inc.
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