PIC24FJ32GA104-I/PT Microchip Technology, PIC24FJ32GA104-I/PT Datasheet - Page 255

• Manufacturer Part Number: PIC24FJ32GA104-I/PT
• Description: 16-bit, 16 MIPS, 32KB Flash, 8KB RAM, Nanowatt XLP 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ32GA104-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.0
The PIC24F instruction set adds many enhancements
to the previous PIC
taining an easy migration from previous PIC MCU
instruction sets. Most instructions are a single program
memory word. Only three instructions require two
program memory locations.
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction. The instruction set is
highly orthogonal and is grouped into four basic
categories:
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
• Control operations
Table 27-1 shows the general symbols used in
describing the instructions. The PIC24F instruction set
summary in Table 27-2 lists all of the instructions, along
with the status flags affected by each instruction.
Most word or byte-oriented W register instructions
(including
operands:
• The first source operand, which is typically a
• The second source operand, which is typically a
• The destination of the result, which is typically a
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value, ‘f’
• The destination, which could either be the file
Most
rotate/shift instructions) have two operands:
• The W register (with or without an address
• The bit in the W register or file register (specified
 2010 Microchip Technology Inc.
Note:
register ‘Wb’ without any address modifier
register ‘Ws’ with or without an address modifier
register ‘Wd’ with or without an address modifier
register, ‘f’, or the W0 register, which is denoted
as ‘WREG’
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
by a literal value or indirectly by the contents of
register, ‘Wb’)
bit-oriented
INSTRUCTION SET SUMMARY
This chapter is a brief summary of the
PIC24F instruction set architecture, and is
not intended to be a comprehensive
reference source.
barrel
®
shift
MCU instruction sets, while main-
instructions
instructions)
(including
have
simple
three
PIC24FJ64GA104 FAMILY
The literal instructions that involve data movement may
use some of the following operands:
• A literal value to be loaded into a W register or file
• The W register or file register where the literal
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register ‘Wb’
• The second source operand, which is a literal
• The destination of the result (only if not the same
The control instructions may use some of the following
operands:
• A program memory address
• The mode of the table read and table write
All instructions are a single word, except for certain
double-word
double-word instructions so that all the required infor-
mation is available in these 48 bits. In the second word,
the 8 MSbs are ‘0’s. If this second word is executed as
an instruction (by itself), it will execute as a NOP.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (uncondi-
tional/computed branch), indirect CALL/GOTO, all table
reads and writes, and RETURN/RETFIE instructions,
which are single-word instructions but take two or three
cycles.
Certain instructions that involve skipping over the sub-
sequent instruction require either two or three cycles if
the skip is performed, depending on whether the
instruction being skipped is a single-word or two-word
instruction. Moreover, double-word moves require two
cycles. The double-word instructions execute in two
instruction cycles.
register (specified by the value of ‘k’)
value is to be loaded (specified by ‘Wb’ or ‘f’)
without any address modifier
value
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
instructions
instructions,
which
DS39951C-page 255
were
made