PIC24HJ32GP202-E/MM Microchip Technology, PIC24HJ32GP202-E/MM Datasheet - Page 146

• Manufacturer Part Number: PIC24HJ32GP202-E/MM
• Description: 16-bit MCU, 32KB Flash,40 MIPS,nanoWatt 28 QFN-S 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ32GP202-E/MM

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24HJ32GP202/204 AND PIC24HJ16GP304
REGISTER 16-1:
DS70289G-page 146
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ACKDT: Acknowledge Data bit (when operating as I
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Send NACK during Acknowledge
0 = Send ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit
(when operating as I
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
0 = Acknowledge sequence not in progress
RCEN: Receive Enable bit (when operating as I
1 = Enables Receive mode for I
0 = Receive sequence not in progress
PEN: Stop Condition Enable bit (when operating as I
1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence
0 = Stop condition not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
0 = Repeated Start condition not in progress
SEN: Start Condition Enable bit (when operating as I
1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence
0 = Start condition not in progress
Hardware clear at end of master Acknowledge sequence
master Repeated Start sequence
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
2
C master, applicable during master receive)
2
C. Hardware clear at end of eighth bit of master receive data byte
2
C master)
2
2
2
C master, applicable during master receive)
C master)
C master)
2
C master)
© 2011 Microchip Technology Inc.