PIC24HJ32GP202-E/MM Microchip Technology, PIC24HJ32GP202-E/MM Datasheet - Page 59

• Manufacturer Part Number: PIC24HJ32GP202-E/MM
• Description: 16-bit MCU, 32KB Flash,40 MIPS,nanoWatt 28 QFN-S 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ32GP202-E/MM

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 6-3:
6.3
The external Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse-width will generate a Reset. Refer
to
minimum pulse-width specifications. The External
Reset (MCLR) Pin (EXTR) bit in the Reset Control
(RCON) register is set to indicate the MCLR Reset.
6.3.1
Many systems have external supervisory circuits that
generate reset signals to Reset multiple devices in the
system. This external Reset signal can be directly con-
nected to the MCLR pin to Reset the device when the
rest of system is Reset.
6.3.2
When using the internal power supervisory circuit to
Reset the device, the external reset pin (MCLR) should
be tied directly or resistively to V
MCLR pin will not be used to generate a Reset. The
external reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.4
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a
special Reset state. This Reset state will not
re-initialize the clock. The clock source in effect prior to
the RESET instruction will remain. SYSRST is released
at the next instruction cycle, and the reset vector fetch
will commence.
© 2011 Microchip Technology Inc.
Section 22.0 “Electrical Characteristics”
SYSRST
SYSRST
SYSRST
External Reset (EXTR)
Software RESET Instruction (SWR)
V
V
V
PIC24HJ32GP202/204 AND PIC24HJ16GP304
DD
DD
DD
EXTERNAL SUPERVISORY CIRCUIT
INTERNAL SUPERVISORY CIRCUIT
V
DD
dips before PWRT expires
BROWN-OUT SITUATIONS
DD
. In this case, the
for
T
BOR
+ T
T
T
PWRT
BOR
BOR
The Software Reset (Instruction) Flag (SWR) bit in the
Reset Control register (RCON<6>) is set to indicate
the software Reset.
6.5
Whenever a Watchdog time-out occurs, the device will
asynchronously assert SYSRST. The clock source will
remain unchanged. A WDT time-out during Sleep or
Idle mode will wake-up the processor, but will not reset
the processor.
The Watchdog Timer Time-out Flag bit (WDTO) in the
Reset Control register (RCON<4>) is set to indicate
the
“Watchdog Timer (WDT)”
Watchdog Reset.
6.6
If
higher-priority trap is being processed, a hard trap
conflict Reset occurs. The hard traps include
exceptions of priority level 13 through level 15,
inclusive. The address error (level 13) and oscillator
error (level 14) traps fall into this category.
The Trap Reset Flag bit (TRAPR) in the Reset Control
register (RCON<15>) is set to indicate the Trap Conflict
Reset. Refer to
more information on trap conflict Resets.
+ T
+ T
a
PWRT
PWRT
Watchdog
lower-priority
Watchdog Time-out Reset (WDTO)
Trap Conflict Reset
Section 7.0 “Interrupt Controller”
Reset.
hard
Refer
V
V
for more information on
V
BOR
trap
BOR
BOR
occurs
DS70289G-page 59
to
Section 19.4
while
for
a