PIC24HJ32GP202-E/MM Microchip Technology, PIC24HJ32GP202-E/MM Datasheet - Page 263

• Manufacturer Part Number: PIC24HJ32GP202-E/MM
• Description: 16-bit MCU, 32KB Flash,40 MIPS,nanoWatt 28 QFN-S 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ32GP202-E/MM

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision G (January 2011)
This revision includes typographical and formatting
changes throughout the data sheet text. In addition, all
instances of V
All other major changes are referenced by their
respective section in the following table.
TABLE A-2:
© 2011 Microchip Technology Inc.
High-Performance, 16-bit Microcontrollers
Section 2.0 “Guidelines for Getting Started
with 16-bit Microcontrollers”
Section 4.0 “Memory Organization”
Section 8.0 “Oscillator Configuration”
Section 18.0 “10-bit/12-bit Analog-to-Digital
Converter (ADC)”
Section 19.0 “Special Features”
PIC24HJ32GP202/204 AND PIC24HJ16GP304
DDCORE
Section Name
MAJOR SECTION UPDATES
have been removed.
Added the SSOP package information (see “Packaging:”,
and
The frequency limitation for device PLL start-up conditions was
updated in
Start-up”.
The second paragraph in
Updated the data memory reference in the third paragraph in
Section 4.2 “Data Address
The All Resets values for the following SFRs in the Timer Register
Map were changed (see
• TMR1
• TMR2
• TMR3
Added Note 3 to the OSCCON: Oscillator Control Register (see
Register
Added Note 2 to the CLKDIV: Clock Divisor Register (see
Register
Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see
Register
Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see
Register
Updated the V
(see
Added a new paragraph and removed the third paragraph in
Section 19.1 “Configuration
Added the column “RTSP Effects” to the Configuration Bits
Descriptions (see
“Pin
Figure 18-1
8-1).
8-2).
8-3).
8-4).
Diagrams”).
Section 2.7 “Oscillator Value Conditions on Device
REFL
and
Table
references in the ADC1 module block diagrams
Figure
Update Description
19-2).
Table
Section 2.9 “Unused I/Os”
18-2).
Space”.
Bits”.
4-5):
DS70289G-page 263
was updated.
Table
1,