S29JL032J70TFI420 Spansion Inc., S29JL032J70TFI420 Datasheet - Page 36

• Manufacturer Part Number: S29JL032J70TFI420
• Description: IC 3V 32M SIMULTANEOUS READ/WRITE FLASH
• Manufacturer: Spansion Inc.

Specifications of S29JL032J70TFI420

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 70ns
• Interface Type: Serial
• Boot Type: Bottom
• Address Bus: 22/21Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 4M/2M
• Supply Current: 16mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Supplier Unconfirmed

10.6
10.7
36
Chip Erase Command Sequence
Sector Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations.
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/
BY#. Refer to
Any commands written during the chip erase operation are ignored. However, note that a hardware reset
immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array data, to ensure data integrity. Note that the Secured
Silicon Region, autoselect, and CFI functions are unavailable when an erase operation is in progress.
Figure 10.2 on page 37
Operations on page 52
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed
by the address of the sector to be erased, and the sector erase command.
address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically programs and verifies the entire sector for an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 80 µs occurs. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may
be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between
these additional cycles must be less than 80 µs, otherwise erasure may begin. Any sector erase address and
command following the exceeded time-out may or may not be accepted. It is recommended that processor
interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be
re-enabled after the last Sector Erase command is written. If any command other than 30h, B0h, F0h is
input during the time-out period, the normal operation will not be guaranteed. The system must rewrite
the command sequence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See
Timer on page
in the command sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data
from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7,
DQ6, DQ2, or RY/BY# in the erasing bank. Refer to
these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands
are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs,
the sector erase command sequence should be reinitiated once that bank has returned to reading array data,
to ensure data integrity. Note that the Secured Silicon Region, autoselect, and CFI functions are unavailable
when an erase operation is in progress.
Figure 10.2 on page 37
Operations on page 52
Write Operation Status on page 40
44.). The time-out begins from the rising edge of the final WE# or CE# pulse (first rising edge)
for parameters, and
for parameters, and
illustrates the algorithm for the erase operation. Refer to
illustrates the algorithm for the erase operation. Refer to
D a t a
S29JL032J
S h e e t
Table 10.1 on page 39
Figure 17.7 on page 54
Figure 17.7 on page 54
for information on these status bits.
Write Operation Status on page 40
( P r e l i m i n a r y )
shows the address and data requirements
for timing diagrams.
for timing diagrams.
Table 10.1 on page 39
S29JL032J_00_03 August 25, 2010
Erase and Program
Erase and Program
DQ3: Sector Erase
for information on
shows the