SST89E58RD2-40-C-TQJE Microchip Technology, SST89E58RD2-40-C-TQJE Datasheet - Page 17
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SST89E58RD2-40-C-TQJE
Manufacturer Part Number
SST89E58RD2-40-C-TQJE
Description
4.5 To 5.5V FlashFlex 8-bit 8051 Microcontroller 44 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
FlashFlex®r
Specifications of SST89E58RD2-40-C-TQJE
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
36
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
8K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
44-TQFP
Processor Series
FlashFlex51
Core
C51
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
5
Number Of Timers
3
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SST89E58RD2-40-C-TQJE
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
SST89E58RD2-40-C-TQJE
Manufacturer:
SST
Quantity:
20 000
FlashFlex MCU
SST89E54RD2A/RDA / SST89E58RD2A/RDA
3.5 Dual Data Pointers
The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data
pointers is accessed. When DPS=0, DPTR0 is selected; when DPS=1, DPTR1 is selected. Quickly switching
between the two data pointers can be accomplished by a single INC instruction on AUXR1. (See Figure 3-4)
3.6 Special Function Registers
Most of the unique features of the FlashFlex microcontroller family are controlled by bits in special function regis-
ters (SFRs) located in the SFR memory map shown in Table 3-4. Individual descriptions of each SFR are provided
and reset values indicated in Tables 3-5 to 3-9.
TABLE
©2008 Silicon Storage Technology, Inc.
FIGURE
1. Bit addressable SFRs
D8H
D0H
C8H
C0H
F8H
F0H
E8H
E0H
B8H
B0H
A8H
A0H
98H
90H
88H
80H
3-4: FlashFlex SFR Memory Map
T2CON
WDTC
CCON
SCON
TCON
PSW
3-4: Dual Data Pointer Organization
ACC
IEA
DPS = 0 → DPTR0
DPS = 1 → DPTR1
IP1
P3
P2
P1
P0
IP
IE
B
1
1
1
1
1
1
1
AUXR1 / bit0
1
1
1
1
1
1
1
1
1
DPS
T2MOD
SADEN
SADDR
CMOD
TMOD
SFCF
SBUF
CH
CL
SP
CCAPM0
CCAP0H
CCAP0L
RCAP2L
AUXR1
SFCM
SPSR
DPL
TL0
DPH
83H
CCAPM1
CCAP1H
RCAP2H
CCAP1L
SFAL
DPH
TL1
8 BYTES
17
DPL
82H
CCAPM2
CCAP2H
CCAP2L
SFAH
TH0
TL2
DPTR1
DPTR0
CCAPM3
CCAP3H
CCAP3L
WDTD
SPCR
SFDT
TH2
TH1
P4
External Data Memory
CCAPM4
CCAP4H
CCAP4L
XICON
SPDR
AUXR
SFST
1339 F06.0
PCON
IP1H
IPH
S71339-02-000
Data Sheet
T3-4.0 1339
FFH
F7H
EFH
E7H
DFH
D7H
CFH
C7H
BFH
B7H
AFH
A7H
9FH
97H
8FH
87H
02/08